ESD protection apparatus
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Ti Su, Shu-Ming Cheng
Life of this patent
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Abstract
An electrostatic discharge (ESD) protection structure comprises a first NPN transistor and a second NPN transistor connected in parallel. The bases of the first NPN transistor and the second NPN transistor are coupled together and further coupled to a first voltage potential and a second voltage potential through two deep trench capacitors respectively. The ESD protection structure further comprises a third deep trench capacitor and a fourth deep trench capacitor coupled between the first voltage potential and the second voltage potential.
Claims20
A device comprising:
- a first NPN transistor comprising:
- a first collector formed in a first semiconductor region;
- a first emitter formed in a second semiconductor region;
- and
- a first base formed in a substrate and coupled to a first capacitor and a second capacitor, wherein:
- the first capacitor is coupled between the base and a first voltage potential;
- and
- the second capacitor is coupled between the base and a second voltage potential;
- a second NPN transistor comprising:
- a second collector formed in a third semiconductor region;
- a second emitter formed in a fourth semiconductor region;
- and
- a second base formed in the substrate and directly connected to the first base;
- a third capacitor coupled between the first voltage potential and the second voltage potential;
- and
- a fourth capacitor coupled between the first voltage potential and the second voltage potential.
An Apparatus comprising:
- a first semiconductor region formed in a substrate, wherein a first conductive region is embedded in the first semiconductor region and a first dielectric layer is formed between the first conductive region and the first semiconductor region;
- a second semiconductor region formed in the substrate, wherein a second conductive region is embedded in the second semiconductor region and a second dielectric layer is formed between the second conductive region and the second semiconductor region, and wherein the second semiconductor region is disposed adjacent to the first semiconductor region and a first implanted region is formed between the first semiconductor region and the second semiconductor region;
- a third semiconductor region formed in the substrate, wherein a third conductive region is embedded in the third semiconductor region and a third dielectric layer is formed between the third conductive region and the third semiconductor region;
- and
- a fourth semiconductor region formed in the substrate, wherein a fourth conductive region is embedded in the fourth semiconductor region and a fourth dielectric layer is formed between the fourth conductive region and the fourth semiconductor region, and wherein the fourth semiconductor region is disposed adjacent to the third semiconductor region and a second implanted region is formed between the third semiconductor region and the fourth semiconductor region.
A semiconductor chip comprising:
- a protection structure having:
- a first transistor comprising:
- a first collector formed in a first semiconductor region;
- a first emitter formed in a second semiconductor region;
- and
- a first base formed in a substrate;
- a second transistor comprising:
- a second collector formed in a third semiconductor region;
- a second emitter formed in a fourth semiconductor region;
- and
- a second base formed in the substrate and coupled to the first base;
- a third capacitor coupled between a first voltage potential and a second voltage potential;
- and
- a fourth capacitor coupled between the first voltage potential and the second voltage potential;
- a low dropout regulator having:
- a first pad electrically coupled to the first collector of the first transistor and the second collector of the second transistor;
- and
- a second pad electrically coupled to the first emitter of the first transistor and the second emitter of the second transistor.
Dependencies are inferred from the claim text.