US 8,941,676 B2 · On-chip anti-alias resolve in a cache tiling architecture

Abstract

One embodiment of the present invention includes a graphics subsystem for processing multi-sample anti-aliasing work. The graphics subsystem includes a cache unit, a tiling unit, and a screen-space pipeline coupled to the cache unit and to the tiling unit. The tiling unit is configured to organize multi-sample anti-aliasing commands into cache tile batches. The screen-space pipeline includes a pixel shader and a raster operations unit, and receives cache tile batches from the tiling unit. The pixel shader is configured to generate sample data based on a set of primitives and to generate resolved data based on the sample data. The raster operations unit is configured to store the sample data in the cache unit and to invalidate the sample data after the pixel shader generates the resolved data.

Claims20

Dependent claims

A graphics subsystem, comprising:

a cache unit;
and
a first screen-space pipeline coupled to the cache unit and including:
a first pixel shader configured to:
generate a first set of sample data based on a first set of primitives, and
generate a first set of resolved data based on the first set of sample data;
and
a first raster operations unit configured to:
store the first set of sample data in a first set of cache lines included in the cache unit, and
invalidate the first set of cache lines in response to the first set of resolved data being generated.

7 more elements

A graphics subsystem, comprising:

a cache unit;
a first screen-space pipeline coupled to the cache unit and including:
a first pixel shader configured to:
generate a first set of sample data associated with a first cache tile that is associated with a first set of pixels, based on a first set of primitives, wherein the first set of sample data is generated based on a second set of pixels that are offset from the first set of pixels based on a cache tile traversal direction, and
apply a multi-pixel filter to the first set of primitives to generate a first set of resolved data for the first set of pixels and associated with the first cache tile;
a first raster operations unit configured to:
store the first set of sample data in a first set of cache lines included in the cache unit, and
invalidate the first set of cache lines after the first set of resolved data is generated, wherein the first set of cache lines corresponds to a third set of pixels that are offset from the first set of pixels based on a direction opposite to the cache tile traversal direction;
a first pre-raster-operation unit configured to:
receive a first barrier command,
in response to receiving the first barrier command, suspend processing so that the first pixel shader is prevented from generating the first set of resolved data, and
in response to receiving a release signal, reinstate processing so that the first pixel shader is able to generate the first set of resolved data;
and
a second screen-space pipeline coupled to the cache unit and including:
a second pixel shader configured to:
generate a second set of sample data associated with the first cache tile based on a second set of primitives, and
generate a second set of resolved data associated with the first cache tile based on the second set of sample data;
a second raster operations unit configured to:
store the second set of sample data in a second set of cache lines included in the cache unit, and
invalidate the second set of cache lines after the second set of resolved data is generated;
and
a second pre-raster-operations unit configured to:
receive a second barrier command,
in response to receiving the second barrier command, suspend processing so that the second pixel shader is prevented from generating the second set of resolved data, and
in response to receiving the release signal, reinstate processing so that the second pixel shader is able to generate the second set of resolved data.

22 more elements

A computing device, comprising:

a graphics subsystem, comprising:
a cache unit;
and
a first screen-space pipeline coupled to the cache unit and including:
a first pixel shader configured to:
generate a first set of sample data based on a first set of primitives, and
generate a first set of resolved data based on the first set of sample data;
and
a first raster operations unit configured to:
store the first set of sample data in a first set of cache lines included in the cache unit, and
invalidate the first set of cache lines in response to the first set of resolved data being generated.

8 more elements

A computing device, comprising:

a graphics subsystem, comprising:
a cache unit;
a first screen-space pipeline coupled to the cache unit and including:
a first pixel shader configured to:
generate a first set of sample data associated with a first cache tile associated with a first set of pixels based on a first set of primitives for a second set of pixels that are offset from the first set of pixels based on a cache tile traversal direction, and
generate a first set of resolved data associated with the first cache tile based on the first set of sample data for the first set of pixels;
a first raster operations unit configured to:
store the first set of sample data in a first set of cache lines included in the cache unit, and
invalidate the first set of cache lines after the first set of resolved data is generated for a third set of pixels that are offset from the first set of pixels based on a direction opposite to the cache tile traversal direction;
and
a first pre-raster-operations unit configured to:
receive a first barrier command,
in response to receiving the first barrier command, suspend processing so that the first pixel shader is prevented from generating the first set of resolved data, and
in response to receiving a release signal, reinstate processing so that the first pixel shader is able to generate the first set of resolved data;
and
a second screen-space pipeline coupled to the cache unit and including:
a second pixel shader configured to:
generate a second set of sample data associated with the first cache tile based on a second set of primitives, and
generate a second set of resolved data associated with the first cache tile based on the second set of sample data;
a second raster operations unit configured to:
store the second set of sample data in a second set of cache lines included in the cache unit, and
invalidate the second set of cache lines after the second set of resolved data is generated;
and
a second pre-raster-operations unit configured to:
receive a second barrier command,
in response to receiving the second barrier command, suspend processing so that the second pixel shader is prevented from generating the second set of resolved data, and
in response to receiving the release signal, reinstate processing so that the second pixel shader is able to generate the second set of resolved data;
and
a back-end unit configured to transmit the release signal to the first pre-raster-operations unit after the first raster operations unit stores the first set of sample data in the first set of cache lines.

26 more elements

Dependencies are inferred from the claim text.

On-chip anti-alias resolve in a cache tiling architecture

Life of this patent

On-chip anti-alias resolve in a cache tiling architecture

Life of this patent

Abstract

Claims20