System and method for efficient resource management of a signal flow programmed digital signal processor code

Logic encoded in non-transitory media that includes instructions for execution and when executed by a processor, is operable to perform operations comprising:

• determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, wherein the connection sequence indicates connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections;
• determining a buffer sequence indicating an order of using a plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence;
• and reusing at least some of the plurality of memory buffers according to the buffer sequence, wherein the determining the buffer sequence comprises:
• constructing a first MLM comprising N rows and M columns, wherein N is the number of the algorithm elements using the memory buffers, and M is the number of the connections;
• arranging the N algorithm elements in an ascending order in the N rows and the M connections in an ascending order in the M columns;
• for each cell in the first MLM, marking a first symbol if the algorithm element corresponding to the row of the cell generates an output on the connection corresponding to the column of the cell, and marking a second symbol if the algorithm element corresponding to the row of the cell receives an input on the connection corresponding to the column of the cell;
• and
• generating a second MLM by rearranging the rows in the first MLM such that in any given column, the first symbol appears before the second symbol.

An apparatus, comprising:

• a memory element for storing data, wherein the memory element comprises a plurality of memory buffers;
• and
• a processor operable to execute instructions associated with the data, wherein the processor and the memory element cooperate, such that the apparatus is configured for:
• determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, wherein the connection sequence indicates connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections;
• determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence;
• and
• reusing at least some of the plurality of memory buffers according to the buffer sequence, wherein the determining the buffer sequence comprises:
• constructing a first MLM comprising N rows and M columns, wherein N is the number of the algorithm elements using the memory buffers, and M is the number of the connections;
• arranging the N algorithm elements in an ascending order in the N rows and the M connections in an ascending order in the M columns;
• for each cell in the first MLM, marking a first symbol if the algorithm element corresponding to the row of the cell generates an output on the connection corresponding to the column of the cell, and marking a second symbol if the algorithm element corresponding to the row of the cell receives an input on the connection corresponding to the column of the cell;
• and
• generating a second MLM by rearranging the rows in the first MLM such that in any given column, the first symbol appears before the second symbol.