Split push buffer rendering for scalability
AssigneeNVIDIA Corporation
InventorHenry P. Moreton
Life of this patent
Estimating the term…
Abstract
Frames are rendered by multiple graphics processors (GPUs), which may be heterogeneous. Graphics processors split the execution of the command in a push buffer of a frame. One GPU begins rendering a frame, and a second GPU takes over rendering that frame after the second GPU is done rendering a previous frame. The second GPU may then begin rendering a subsequent frame.
Claims20
A method of rendering pixels for a plurality of frames with a plurality of graphics processors configured to operate in parallel, the method comprising:
- providing, with a command buffer, commands for rendering pixels for a plurality of current frames;
- and
- for each current frame:
- rendering a first portion of a plurality of pixels for the current frame with a first graphics processor by providing, with the command buffer, a first portion of the commands for rendering the plurality of pixels for the current frame to the first graphics processor, and executing, with the first graphics processor, the first portion of the commands for rendering the plurality of pixels for the current frame;
- after a second graphics processor completes a rendering of a previous frame, rendering a second portion of the plurality of pixels for the current frame with the second graphics processor by providing, with the command buffer, a remaining portion of the commands for rendering the plurality of pixels for the current frame to the second graphics processor, and executing, with the second graphics processor, the remaining portion of the commands for rendering the plurality of pixels for the current frame;
- and
- rendering, with the first graphics processor, a first portion of a plurality of pixels for a subsequent frame while the second graphics processor completes rendering the second portion of the plurality of pixels for the current frame.
A computer program product comprising a non-transitory computer readable medium encoded with program code for controlling operation of a computer system to render a plurality of frames with a plurality of graphics processors configured to operate in parallel, the program code including:
- program code for generating pixels by providing commands for rendering a plurality of current frames with a command buffer;
- and
- for each current frame:
- program code for rendering a first portion of a plurality of pixels for the current frame with a first graphics processor by providing, with the command buffer, a first portion of commands for rendering the plurality of pixels for the current frame to the first graphics processor, and executing, with the first graphics processor, the first portion of the commands for rendering the plurality of pixels for the current frame;
- program code for rendering a second portion of the plurality of pixels for the current frame with a second graphics processor by for providing, with the command buffer and after the second graphics processor has completed rendering a previous frame, a remainder of the commands for rendering the plurality of pixels for the current frame to the second graphics processor, and executing, with the second graphics processor, the remaining portion of the commands for rendering the plurality of pixels for the current frame;
- and
- program code for rendering executing, with the first graphics processor, a first portion of a plurality of pixels for a subsequent frame while the second graphics processor completes rendering the second portion of the plurality of pixels for the current frame.
A method of rendering pixels for a plurality of frames with a plurality of graphics processors configured to operate in parallel, the method comprising:
- providing, with a command buffer, commands for rendering a first plurality of pixels for a first frame and commands for rendering a second plurality of pixels for a second frame;
- rendering, with a first graphics processor, a first portion of the first plurality of pixels by executing a first portion of the commands for rendering the first plurality of pixels for the first frame;
- providing, with a second graphics processor, a signal to the first graphics processor indicating the availability of the second graphics processor;
- and
- after receiving the signal from a second graphics processor indicating the availability of the second graphics processor:
- rendering, with the first graphics processor, a first portion of the second plurality of pixels by executing a first portion of the commands for rendering the second frame;
- and
- rendering, with the second graphics processor, a second portion of the first plurality of pixels by executing a remaining portion of the commands for rendering the first plurality of pixels for the first frame while the first graphics processor renders the first portion of the second plurality of pixels for the second frame.
Dependencies are inferred from the claim text.