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US 8,941,575 B2Granted
Timing controller for display
AssigneeShanghai Tianma Micro-Electronics Co., Ltd.
InventorsLing Shen, Yuan Li
Life of this patent
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Abstract
According to one embodiment of the present invention, a timing controller for a display, includes a first unit, a second unit and a third unit. The first unit is configured to generate an image signal from a first input signal. The second unit is configured to generate a multitude of timing signals and a control signal from a multitude of second input signals, the control signal being generated after the multitude of timing signals are generated. The third unit is configured to generate a multitude of first signals from the multitude of timing signals after receipt of the control signal from the second unit. The image signal and the multitude of first signals are configured to drive the display when the timing controller is connected to the display.
Claims15
A timing controller for a display, comprising:
- a first unit configured to generate an image signal from a first input signal;
- a second unit configured to generate a plurality of timing signals and a control signal from a plurality of second input signals, the control signal being generated after the plurality of timing signals are generated;
- and
- a third unit configured to generate a plurality of first signals from the plurality of timing signals after receipt of the control signal from the second unit, wherein the image signal and the plurality of first signals are configured to drive the display when the timing controller is connected to the display,
- wherein the plurality of timing signals comprise a horizontal display period, a horizontal synchronization cycle, a horizontal synchronization interval, a vertical display period, a vertical synchronization cycle and a vertical synchronization interval, the plurality of second input signals comprise at least an enabling signal and a clock signal, and the second unit comprises:
- a fourth unit configured to generate a first count of the clock signal during a first level of the enabling signal, the first count representing the horizontal display period;
- a fifth unit, connected with the fourth unit, configured to generate a second count of the clock signal during a second level of the enabling signal, the second level being different than the first level, the second count representing the horizontal synchronization interval when the second count is smaller than the first count;
- a sixth unit, connected with the fourth unit, configured to generate a third count of the clock signal during the second level of the enabling signal, the third count representing the vertical synchronization interval when the third count is larger than the first count;
- a seventh unit, connected with the fourth unit and the fifth unit, configured to sum the first count and the second count thereby representing the horizontal synchronization cycle;
- an eighth unit, connected with the fourth unit and the sixth unit, configured to generate a fourth count of the clock signal during the first count for a period of time taken by the sixth unit to obtain the third count twice, the fourth count representing the vertical display period;
- and
- a ninth unit, connected with the eighth unit and the sixth unit, configured to sum the fourth count and the third count thereby representing the vertical synchronization cycle.
9 more elements
A method for controlling timing signals to a display by a timing controller, the method comprising:
- generating an image signal from a first input signal;
- generating a plurality of timing signals from a plurality of second input signals;
- generating a control signal from the plurality of second input signals after the plurality of timing signals are generated;
- generating a plurality of first signals from the plurality of timing signals after receipt of the control signal;
- and
- driving the display by the timing controller when the image signal and the plurality of first signals are connected to the display,
- wherein the plurality of timing signals comprise a horizontal display period, a horizontal synchronization cycle, a horizontal synchronization interval, a vertical display period, a vertical synchronization cycle and a vertical synchronization interval, the plurality of second input signals comprise at least an enabling signal and a clock signal, and generating the plurality of timing signals from the plurality of second input signals comprises:
- generating a first count of the clock signal during a first level of the enabling signal, the first count representing the horizontal display period;
- generating a second count of the clock signal during a second level of the enabling signal, the second level being different than the first level, the second count representing the horizontal synchronization interval when the second count is smaller than the first count;
- generating a third count of the clock signal during the second level of the enabling signal, the third count representing the vertical synchronization interval when the third count is larger than the first count;
- summing the first count and the second count thereby representing the horizontal synchronization cycle;
- generating a fourth count of the clock signal during the first count for a period of time taken by the sixth unit to obtain the third count twice, the fourth count representing the vertical display period;
- and
- summing the fourth count and the third count thereby representing the vertical synchronization cycle.
11 more elements
Dependencies are inferred from the claim text.