US 8,941,430 B2 · Timing calibration for on-chip interconnect

Abstract

One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.

Claims22

Dependent claims

A method for calibrating an on-chip interconnect, comprising:

applying a first signal transition pattern that is a first binary pattern to a first wire of the on-chip interconnect that is coupled between a first transmitter and a first receiver to generate a plurality of first measurements that correspond to a timing characteristic of the first wire;
and
configuring, based on the plurality of first measurements, a delay circuit to adjust a delay of the first wire to fall within a range of a predetermined delay variation that is substantially centered on an edge of a clock signal.

An on-chip interconnect calibration system, comprising:

a calibration pattern generation unit configured to generate a first signal transition pattern that is a first binary pattern;
a calibration pattern capture unit configured to generate a plurality of first measurements that correspond to a timing characteristic of a first wire of the on-chip interconnect that is coupled between a first transmitter and a first receiver;
a delay circuit that is coupled to the first wire of the on-chip interconnect;
and
a calibration control unit that is coupled to the calibration pattern generation unit and a calibration pattern capture unit and configured to:
apply the first signal transition pattern to the first wire of the on-chip interconnect to generate the plurality of first measurements;
and
configure, based on the plurality of first measurements, the delay circuit to adjust a delay of the first wire to fall within a range of a predetermined delay variation that is substantially centered on an edge of a clock signal.

5 more elements

Dependencies are inferred from the claim text.

Timing calibration for on-chip interconnect

Life of this patent

Timing calibration for on-chip interconnect

Life of this patent

Abstract

Claims22