Master-slave flip-flop with low power consumption

A method of operating a flip-flop, said flip-flop comprising a master latch having first and second three-state stages respectively having a first pair of complementary semiconductor devices gated by a data input of said first three-state stage and a second pair of complementary semiconductor devices gated by a data input of said second three-state stage, and a first feedback stage for positive feedback from data outputs of said first and second three-state stages to said data input of said second three-state stage, and a slave latch connected to said master latch, said slave latch having third and fourth three-state stages having respectively a third pair of complementary semiconductor devices gated by a data input of said third three-state stage and a fourth pair of complementary semiconductor devices gated by a data input of said fourth three-state stage, and a second feedback stage for positive feedback from data outputs of said third and fourth three-state stages to said data input of said fourth three-state stage, the method comprising:

• applying a data input signal to said data input of said first three-state stage;
• applying a clock input signal to first and second clock switches, wherein the first clock switch that receives clock signals from a clock signal source is configured in one of said first and fourth three-state stages, and the other one of said first and fourth three-state stages shares the first clock switch, and a second clock switch that receives clock signals from said clock signal source is configured in one of said second and third three-state stages, and the other of said second and third three-state stage shares the second clock switch, wherein the first and second clock switches have opposite phases, and wherein the second three-state stage further includes an additional pair of complementary semiconductor devices having signal paths connected in series with each other and both being gated by a data output of said slave latch.