Low power latching circuits

A method of updating a value stored in a master slave flip flop, said master slave flip flop comprising a master latch and a slave latch each having feedback loops for holding said data value, each feedback comprising a set of two switching devices arranged in parallel on said feedback loop and configured such that either one of said two switching devices is on at any one time and completes said feedback loop, and access control devices for controlling access to said feedback loops, said access control devices being configured to provide said access on different phases of a clock cycle, said method comprising the steps of:

• receiving a data value that is different to a data value currently stored;
• providing at least one control signal from said data value and transmitting said at least one control signal to said set of two switching devices arranged on a feedback loop of said master and said slave latches;
• switching one of said switching devices in each set on and an other off in response to said at least one control signal;
• in response to said clock signal transmitting said data value via an access control device to said feedback loop of said master latch;
• updating said data value stored in said master latch;
• in response to said clock signal changing phase transmitting said updated data value from said master latch to said slave latch;
• and
• updating said data value held in said slave latch.

A flip flop comprising a first latching circuit and a second latching circuit, each of said first latching circuit and said second latching circuit for receiving and holding a data value, and each of said first latching circuit and said second latching circuit comprising:

• a feedback loop comprising two inverting means for inverting a signal arranged in a feedback loop, an output of a first inverting means being connected to an input of a second inverting means at a first portion of said feedback loop, said first portion holding said data value and an output of said second inverting means being connected to an input of said first inverting means at a second portion of said feedback loop, said second portion holding a complementary data value;
• a first input means for receiving a data value;
• an output means for outputting a value indicative of said data value from said feedback loop;
• a clock signal input means for receiving a clock signal;
• an access control means for connecting or isolating said first input means from said first portion of said feedback loop in dependence upon a value of said clock signal;
• wherein
• said feedback loop comprises two switching means arranged in parallel at one of said first or said second portion of said feedback loop, said switching means providing a connection between said inverting means at said one of said first or second portion of said feedback loop, while an other of said second or first portion comprises a conducting means for providing a permanent connection between said inverting means;
• each of said latching circuits comprises control signal means for providing at least one control signal for controlling said two switching means, said two switching means and said control signal means being configured such that in response to said at least one control signal transmitted from said control signal means one of said two switching means is on and provides said connection between said inverting means and said other of said two switching means is off;
• wherein
• said control signal means is for providing said at least one control signal in dependence upon said data value such that in response to said data value changing said at least one control signal changes and one of said two switching means that is currently on changes to said other of said two switching means and said switching means that turns on and said access control means act together to update said data value within said feedback loop,
• wherein said output of said first latching circuit is connected to said first portion of said feedback loop and is configured to output said data value and said access control means of said second latching circuit is connected to said output of said first latching circuit, and said access control means of said first latching circuit and said access control means of said second latching circuit are configured to operate on different phases of said clock cycle such that one is open when the other is closed.