Extending a clock frequency range of a critical path monitor

A computer usable program product comprising a computer usable storage device including computer usable code for extending a clock frequency range of a critical path monitor (CPM), the computer usable code comprising:

• computer usable code for configuring, in an integrated circuit (IC), the CPM, wherein the IC includes a set of critical paths, wherein the CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector;
• computer usable code for configuring the edge detector with a set of edge detector latches;
• computer usable code for configuring a set of set-reset (SR) latches, wherein an edge detector latch in the set of edge detector latches is associated with a corresponding SR latch in the set of SR latches;
• computer usable code for configuring a reset signal to reach the set of edge detector latches in an offset synchronization with a latch clock signal used in the set of edge detector latches;
• and
• computer usable code for configuring the CPM to operate using a frequency of the latch clock signal such that the frequency is higher than a threshold frequency.

A method for extending a clock frequency range of a critical path monitor (CPM), the method comprising:

• configuring, in an integrated circuit (IC), the CPM, wherein the IC includes a set of critical paths, wherein the CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector;
• configuring the edge detector with a set of edge detector latches;
• configuring sending a signal through the split path, wherein the signal is delayed by a first amount of time in a first portion of the split path, wherein the signal is further delayed reaching each edge detector latch in the set of edge detector latches by a different second amount of time;
• configuring each edge detector latch in the set of edge detector latches to capture the signal when a rising edge of the signal arrives at the edge detector latch;
• and
• configuring each edge detector latch in the set of edge detector latches to reset when a falling edge of the signal arrives at the edge detector latch.