Digital phase locked loop with reduced convergence time

A digital phase locked loop comprising:

• a digital controlled oscillator configured to produce an output signal having a frequency;
• a phase comparator configured to compare said output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal;
• a loop filter configured to produce a control signal for said digital controlled oscillator from an output of said phase comparator, said loop filter comprising a proportional part producing a proportional component of said control signal, an integral part producing an integral component of said control signal, and an adder configured to receive said respective proportional and integral components at first and second inputs thereof to produce said control signal, said integral part including a delayed feedback loop normally configured to accept said integral component at an input thereof;
• a first switch for replacing said integral component at the input of said delayed feedback loop by said control signal in response to an activation signal;
• and
• a control module configured to produce said activation signal to activate said switch for brief periods when the phase error is non-zero and the rate of change of phase is less than a threshold value.