Semiconductor device

A semiconductor device comprising:

• first and second wirings configured to be applied with first and second constant potentials, respectively;
• an input terminal and an output terminal;
• first to eighth transistors each comprising a first terminal, a second terminal, and a gate;
• and
• a capacitor comprising first and second electrodes,
• wherein:
• the first terminal, the second terminal, and the gate of the first transistor are electrically connected to the first wiring, the output terminal, and the second terminal of the fifth transistor, respectively;
• the first terminal, the second terminal, and the gate of the second transistor are electrically connected to the second wiring, the output terminal, and the input terminal, respectively;
• the first terminal, the second terminal, and the gate of the third transistor are electrically connected to the first wiring, the second electrode, and the second terminal of the fifth transistor, respectively;
• the first terminal, the second terminal, and the gate of the fourth transistor are electrically connected to the second wiring, the second electrode, and the input terminal, respectively;
• the first terminal and the gate of the fifth transistor are electrically connected to the second wiring and the first terminal of the eighth transistor;
• the first terminal, the second terminal, and the gate of the sixth transistor are electrically connected to the input terminal, the gate of the eighth transistor, and the first wiring, respectively;
• the first terminal, the second terminal, and the gate of the seventh transistor are electrically connected to the input terminal, the first terminal of the eighth transistor, and the first wiring, respectively;
• the second terminal of the eighth transistor is electrically connected to the first wiring;
• and
• the first electrode is electrically connected to the input terminal.

A semiconductor device comprising:

• first and second wirings configured to be applied with first and second constant potentials, respectively;
• a third wiring;
• an output terminal;
• first to sixth transistors each comprising a first terminal, a second terminal, and a gate;
• and
• an inverter circuit,
• wherein:
• the first terminal, the second terminal, and the gate of the first transistor are electrically connected to the third wiring, the output terminal, and the second terminal of the fourth transistor, respectively;
• the first terminal, the second terminal, and the gate of the second transistor are electrically connected to the second wiring, the output terminal, and the inverter circuit, respectively;
• the first terminal, the second terminal, and the gate of the third transistor are electrically connected to the second wiring, the second terminal of the fourth transistor, and the inverter circuit, respectively;
• the first terminal and the gate of the fourth transistor are electrically connected to each other;
• the first terminal, the second terminal, and the gate of the fifth transistor are electrically connected to the second wiring, the second terminal of the fourth transistor, and the gate of the sixth transistor, respectively;
• and
• the first terminal and the second terminal of the sixth transistor are electrically connected to the first wiring and the inverter circuit, respectively.

A semiconductor device comprising:

• a first wiring;
• a second wiring configured to be applied with a first constant potential;
• first and second output terminals;
• first to sixth transistors each comprising a first terminal, a second terminal, and a gate;
• and
• an inverter circuit,
• wherein:
• the first terminal, the second terminal, and the gate of the first transistor are electrically connected to the first wiring, the second output terminal, and the second terminal of the fourth transistor, respectively;
• the first terminal, the second terminal, and the gate of the second transistor are electrically connected to the second wiring, the first output terminal, and the inverter circuit, respectively;
• the first terminal, the second terminal, and the gate of the third transistor are electrically connected to the second wiring, the second terminal of the fourth transistor, and the inverter circuit, respectively;
• the first terminal and the gate of the fourth transistor are electrically connected to each other;
• the first terminal and the second terminal of the fifth transistor are electrically connected to the second wiring and the second terminal of the fourth transistor, respectively;
• and
• the first terminal, the second terminal, and the gate of the sixth transistor are electrically connected to the first wiring, the first output terminal, and the second terminal of the fourth transistor, respectively.