Edge selection techniques for correcting clock duty cycle

A circuit for generating a clock signal, comprising:

• a multiplexer circuit to selectively output one of a plurality of input clock signals;
• an edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is directly connected to an output of the multiplexer circuit, wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop is directly connected to a select control port of the multiplexer circuit, and
• a clock phase definition circuit that generates the data signal which is input to the data input port of the edge-triggered flip-flop, wherein the data signal is a clock signal having a frequency equal to a frequency of the input clock signals,
• wherein the edge-triggered flip-flop detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port, and
• wherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which output clock signal is directly input to the select control port of the multiplexer circuit.