Semiconductor package including semiconductor chip with through opening
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Cheol Lee, Hyun-Jun Kim, In-Young Lee, Ki-Kwon Jeong
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AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Cheol Lee, Hyun-Jun Kim, In-Young Lee, Ki-Kwon Jeong
Estimating the term…
A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.
A semiconductor package comprising:
A semiconductor package comprising:
A semiconductor package comprising:
Dependencies are inferred from the claim text.
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Characterised by their insulating layers or insulating parts: shapes or dispositions thereof
Package configurations
Manufacture or treatment: using moulds
Encapsulations, e.g. protective coatings: characterised by their shape or disposition
About 6 years 6 months of term left · ends 7 May 2033 (estimated)
This application claims priority, and all the benefits accruing therefrom under 35 U.S.C. 119, from Korean Patent Application No. 10-2011-0110078 filed on Oct. 26, 2011 in the Korean Intellectual Property Office, the contents of are herein incorporated by reference in their entirety.
1. Field
Apparatuses and methods consistent with exemplary embodiments relate to a semiconductor package including a semiconductor chip with a through opening.
The above and/or other exemplary aspects and features will become more apparent by describing in detail exemplary embodiments with reference to the attached drawings, in which:
FIG. 1 is a cross-sectional view showing a semiconductor package in accordance with a first exemplary embodiment;
FIG. 2 is a perspective view of a substrate of FIG. 1;
Advantages and features of exemplary embodiments and methods of accomplishing the same may be understood more readily by reference to the following detailed description and the accompanying drawings. Exemplary embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “connected to,” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from exemplary embodiments.