Wafer level semiconductor package and manufacturing methods thereof

#1. Field of the Invention

#The invention relates generally to semiconductor packages and manufacturing methods thereof. More particularly, the invention relates to a wafer level semiconductor package and manufacturing methods thereof.

#2. Description of Related Art

#FIG. 1 is a cross section view of a stacked package assembly, according to an embodiment of the invention;

#FIG. 2 is a top cross section view of a semiconductor package in a plane A-A shown in FIG. 1, according to an embodiment of the invention;

#FIG. 3 is a cross section view of various conductive via embodiments within an interposer;

#The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of some embodiments of the invention. Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer to the same or like features.

#Referring to FIG. 1, a cross section view is shown of a stacked package assembly 100 according to an embodiment of the invention. The stacked package assembly 100 includes a semiconductor package 192 and a semiconductor package 194 positioned above the semiconductor package 192. The semiconductor package 194 is electrically connected to the semiconductor package 192 through conductive bumps 193. It is contemplated that the semiconductor package 194 may be any form of semiconductor package, such as a wafer-level package, a BGA package, and a substrate-level package. The semiconductor package 194 may also include a combination of one or more semiconductor packages and/or one or more passive electrical components. The semiconductor package 192 includes a semiconductor device 102, which includes a lower surface 104 which in the illustrated embodiment is an active surface, i.e. the active surface having die bond pads 111, an upper surface 106, and lateral surfaces 108 disposed adjacent to a periphery of the semiconductor device 102 and extending between the lower surface 104 and the upper surface 106. In the illustrated embodiment, each of the surfaces 104, 106, and 108 is substantially planar, with the lateral surfaces 108 having a substantially orthogonal orientation with respect to the lower surface 104 or the upper surface 106, although it is contemplated that the shapes and orientations of the surfaces 104, 106, and 108 can vary for other implementations. In one embodiment, the upper surface 106 is a back surface of the semiconductor device 102, while the lower surface 104 is an active surface of the semiconductor device 102. The lower surface 104 may include the die bond pads 111 that provide input and output electrical connections for the semiconductor device 102 to conductive structures included in the package 192, such as a patterned conductive layer 150 (described below). In the illustrated embodiment, the semiconductor device 102 is an integrated circuit, although it is contemplated that the semiconductor device 102, in general, can be any active device including for example an optical or other type of sensor, a micro electro-mechanical system (MEMS), any passive device, or a combination thereof. The semiconductor device 102 may be an active die. While one semiconductor device is shown in the semiconductor package 192, it is contemplated that more than one semiconductor device can be included in the semiconductor package 192 for other implementations.

#As shown in FIG. 1, the package 192 also includes a package body 114 that is disposed adjacent to the semiconductor device 102. In the illustrated embodiment, the package body 114 covers or encapsulates portions of the semiconductor device 102 and portions of one or more interposers 170, such as interposer elements 170 (described below). The package body 114 can provide mechanical stability as well as protection against oxidation, humidity, and other environmental conditions. In this embodiment, the package body 114 substantially covers the upper surface 106 and the lateral surfaces 108 of the semiconductor device 102, with the lower surface 104 of the semiconductor device 102 being substantially exposed or uncovered by the package body 114. The package body 114 includes a lower surface 116 and an upper surface 118. In the illustrated embodiment, each of the surfaces 116 and 118 is substantially planar, although it is contemplated that the shapes and orientations of the surfaces 116 and 118 can vary for other implementations.