Passivation for group III-V semiconductor devices having a plated metal layer over an interlayer dielectric layer

A semiconductor device, comprising:

• a Group III-V semiconductor substrate;
• a first metal layer over the substrate;
• a planarizing interlayer dielectric layer over the first metal layer;
• a first passivation layer over the interlayer dielectric layer, the first passivation layer and the interlayer dielectric layer defining a via extending therethrough to the first metal layer;
• a second metal layer, greater in thickness than the first metal layer, on the first passivation layer, the second metal layer comprising an interconnect extending through the via into contact with the first metal layer, the second metal layer patterned to define at least one conductor;
• and a second passivation layer over the second metal layer and the first passivation layer, the second passivation layer comprising stacked regions of dielectric material, ones of regions under tensile stress alternating with ones of the regions under compressive stress, such that the second passivation layer is subject to net compressive stress.