Integrated circuit using deep trench through silicon (DTS)

A radio frequency area of an integrated circuit, comprising:

• a substrate having a first resistance, the substrate including an implant region;
• a buried oxide layer disposed over the substrate;
• an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance;
• a silicon layer disposed over the buried oxide layer;
• a shallow trench isolation extending from an upper surface of the silicon layer to the buried oxide layer, the shallow trench isolation terminating at the buried oxide layer;
• and
• an interlevel dielectric disposed in a deep trench and engaging an uppermost sidewall of the silicon layer, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region, the deep trench having substantially vertical sidewalls extending from the top surface of the silicon layer to the bottom of the deep trench.