Semiconductor device
AssigneePS4 Luxco S.a.r.l.
InventorYohei Ota
Life of this patent
Estimating the term…
Abstract
Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant.
Claims16
A semiconductor device comprising:
- a memory cell region including a first isolation region, and a first active region provided so as to be divided off by the first isolation region;
- a peripheral region including a second isolation region, and a second active region divided off by the first and second isolation regions, the second active region being formed as a plurality of parallelogram-shaped unit patterns arranged adjacent to each other in a first direction, adjoining sides of the parallelogram-shaped unit patterns being offset from each other, other sides of the parallelogram-shaped unit patterns being parallel to each other in a second direction having an acute angle with respect to the first direction;
- and
- a first wiring buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a third direction perpendicular to the first direction.
A semiconductor device comprising:
- a memory cell region including a first isolation region, and a first active region provided so as to be divided off by the first isolation region;
- a peripheral region including a second isolation region, and a second active region, the second active region being formed as a plurality of parallelogram-shaped unit patterns arranged adjacent to each other in a first direction, adjoining sides of the parallelogram-shaped unit patterns being offset from each other, other sides of the parallelogram-shaped unit patterns being parallel to each other in a second direction having an acute angle with respect to the first direction;
- and
- a first wiring buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a third direction perpendicular to the first direction,
- wherein the second active region is arranged so as to have contact with the first and second isolation regions through part of a side surface of the second active region and so as to surround the memory cell region.
A semiconductor device comprising:
- a memory cell region including a plurality of cell isolation regions which are provided in a semiconductor substrate and extend in a second direction, the cell isolation regions being formed by burying an insulating film in the semiconductor substrate, and a plurality of cell active regions divided off by the plurality of cell isolation regions and extending in the second direction;
- a peripheral region including a peripheral active region surrounding the memory cell region, and a peripheral isolation region arranged in contact with the peripheral active region outside the memory cell region, the peripheral active region being formed as a plurality of parallelogram-shaped unit patterns arranged adjacent to each other in a first direction, adjoining sides of the parallelogram-shaped unit patterns being offset from each other, other sides of the parallelogram-shaped unit patterns being parallel to each other in a second direction having an acute angle with respect to the first direction;
- and
- a plurality of buried word lines which intersect with the plurality of cell active regions and the peripheral active region and extend in a third direction perpendicular to the first direction, the plurality of buried word lines being formed by burying a metal layer in the semiconductor substrate,
- wherein
- a plan-view area of a region in which each of the buried word lines and the peripheral active region intersect with each other is larger than a plan-view area of a region in which each of the buried word lines and each of the plurality of cell active regions intersect with each other.
Dependencies are inferred from the claim text.