Reliable surface mount integrated power module

A method of manufacturing a surface-mount packaging and interconnect structure comprising:

• constructing a sub-module including at least one semiconductor device and a packaging structure formed thereabout, wherein constructing the sub-module comprises:
• attaching the at least one semiconductor device to a dielectric layer;
• forming a first-level metallic interconnect structure over the dielectric layer, the first-level metallic interconnect structure extending through vias in the dielectric layer to electrically connect to the at least one semiconductor device;
• and
• forming a second level input/output (I/O) connection on the dielectric layer on a side opposite the at least one semiconductor device, the second level I/O connection configured to connect the sub-module to an external circuit;
• forming a substrate structure that includes a center substrate layer and first and second metallic layers on opposing sides of the center substrate layer, such that the first and second metallic layers form a first surface and a second surface, respectively, of the substrate structure;
• attaching the sub-module to the first surface of the substrate structure;
• and
• providing a dielectric filler material between the dielectric layer and the first surface of the substrate structure, the dielectric filler material being provided at least partially about the at least one semiconductor device of the sub-module.

A power overlay (POL) packaging structure comprising:

• a POL sub-module, the POL sub-module comprising:
• a dielectric layer;
• a plurality of semiconductor devices attached to the dielectric layer;
• a first level interconnect structure electrically coupled to the plurality of semiconductor devices, the first level interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of semiconductor devices;
• and
• a second level interconnect structure to electrically couple the POL sub-module to an external circuit structure, the second level interconnect structure comprising a plurality of solder bumps formed over the dielectric layer and first level interconnect structure and configured to make an interconnection to the external circuit structure;
• a multi-layer substrate structure having a first surface and a second surface, wherein the plurality of semiconductor devices of the POL sub-module is attached to the first surface of the multi-layer substrate structure, and wherein the multi-layer substrate structure includes:
• a first direct bond copper (DBC) layer forming the first surface of the multi-layer substrate structure;
• a second DBC layer forming the second surface of the multi-layer substrate structure;
• and
• a ceramic layer sandwiched between the first and second DBC layers;
• and
• a dielectric filler material positioned between the dielectric layer and the first surface of the multi-layer substrate structure and at least partially about the plurality of semiconductor devices of the sub-module.