Back to results
US 8,941,181 B2Granted
Compensated well ESD diodes with reduced capacitance
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
Life of this patent
Estimating the term…
Abstract
An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
Claims4
An integrated circuit, comprising:
- a p-type substrate;
- a first p-well formed in said p-type substrate where doping of said first p-well is higher than doping of said p-type substrate;
- an NMOS transistor with N+ doped deep source and drain diffusions formed in said first p-well;
- a first n-well formed in said p-type substrate;
- a PMOS transistor with P+ doped deep source and drain diffusions formed in said first n-well;
- a shallow trench isolation geometry which isolates an N+ deep diffusion from a P+ deep diffusion where said N+ deep diffusion and said N+ doped deep source and drain diffusion doping concentrations are equal and where said P+ deep diffusion and said P+ doped deep source and drain diffusion doping concentrations are equal;
- and
- a low capacitance STI ESD P/N diode formed between said N+ deep diffusion and said p-type substrate where said p-type substrate is under said N+ deep diffusion, where a second p-well is under said P+ deep diffusion;
- where said N+ deep diffusion is connected to a cathode of said low capacitance STI ESD P/N diode;
- where said P+ deep diffusion is connected to an anode of said low capacitance STI ESD P/N diode;
- and
- where said cathode of said low capacitance STI ESD P/N diode is coupled to an I/O pin, and where said anode of said low capacitance STI ESD P/N diode is coupled to Vss or ground.
9 more elements
An integrated circuit, comprising:
- a p-type substrate;
- a p-well formed in said p-type substrate where doping of said p-well is higher than doping of said p-type substrate;
- an NMOS transistor with N+ doped deep source and drain diffusions formed in said p-well;
- a first n-well formed in said p-type substrate;
- a PMOS transistor with P+ doped deep source and drain diffusions formed in said first n-well;
- a shallow trench isolation geometry which isolates an N+ deep diffusion from a P+ deep diffusion where said N+ deep diffusion and said N+ doped deep source and drain diffusion doping concentrations are equal and where said P+ deep diffusion and said P+ doped deep source and drain diffusion doping concentrations are equal;
- and
- a low capacitance STI ESD N/P diode formed between a second nwell and an isolated p-well where said isolated p-well is formed in said second n-well, where said P+ deep diffusion forms a contact diffusion to said isolated p-well, and where said N+ deep diffusion forms a contact diffusion to said second n-well;
- where said N+ deep diffusion is connected to a cathode of said low capacitance STI ESD N/P diode;
- where said P+ deep diffusion is connected to an anode of said low capacitance STI ESD N/P diode;
- and
- where said cathode of said low capacitance STI ESD N/P diode is coupled to Vdd;
- and where said anode of said low capacitance STI ESD N/P diode is coupled to an I/O pin.
10 more elements
Dependencies are inferred from the claim text.