US 8,941,176 B2 · Integrated device with raised locos insulation regions and process for manufacturing such device

Abstract

An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. Formed in the second active area is a power component, which includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region, arranged between the body region and the drain-contact region and having a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Claims17

Dependent claims

A semiconductor device, comprising:

a drain region having a boundary with first and second non coplanar portions;
a body region disposed in the drain region;
a source region disposed in the body region;
a gate insulator disposed over the body region and over the first portion of the boundary;
a gate region disposed over the gate insulator;
and
a thermally oxidized isolation region disposed over the drain region and over the second portion of the boundary, the oxidized isolation region including a first portion extending into the drain region and a second portion larger than the first portion extending above the drain region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/893,269Filed 29 Sep 2010

Priority

IT TO2009A073729 Sep 2009

Published

US 2011/0073960 A131 Mar 2011

Granted

27 Jan 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
H10D 30/65
Double-diffused metal-oxide semiconductor [DMOS] FETs: lateral dmos [ldmos] fets
H10D 64/516
Characterised by the insulating layers: the thicknesses being non-uniform

Integrated device with raised locos insulation regions and process for manufacturing such device

Life of this patent

Integrated device with raised locos insulation regions and process for manufacturing such device

Life of this patent

Abstract

Claims17