Power array with staggered arrangement for improving on-resistance and safe operating area
AssigneeUnited Microelectronics Corp.
InventorsWei-Lin Chen, Ke-Feng Lin, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang, Hsuan-Po Liao
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Abstract
A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
Claims6
A power array with a staggered arrangement for improving on-resistance and safe operating area, comprising:
- two or more rows, wherein each said row comprises a plurality of parallel device units arranged along said row, each said device unit comprises a source region, a drain region, and a gate disposed between said source region and said drain region, wherein each said drain region is offset in a row direction from adjacent said drain region of adjacent said row, and each said gate is offset in said row direction from adjacent said gate of adjacent said row.
Dependencies are inferred from the claim text.