Capacitorless memory device

A capacitorless memory device comprising:

• a bit line on a substrate;
• first and second capacitorless memory cells, the first and second capacitorless memory cells each including,
• a read transistor including,
• a first impurity layer, a second impurity layer, and a third impurity layer stacked in a vertical direction on the bit line,
• the first and third impurity layers being a first conductive type,
• the second impurity layer being a second conductive type that is different from the first conductive type, and
• a write transistor including,
• a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate,
• the source layer being adjacent to a side surface of the second impurity layer of the read transistor, and
• a gate line that is adjacent to a side surface of the body layer and spaced apart from the side surface of the body layer,
• wherein the first impurity layer is between the gate line and the bit line in the vertical direction.

A capacitorless memory device comprising:

• a bit line;
• a ground line;
• a data word line;
• and
• at least one capacitorless memory cell including,
• a read transistor on the bit line, the read transistor including,
• a source structure electrically connected to the bit line,
• a drain structure electrically connected to the ground line,
• a body structure between the source and drain structures, and
• a write transistor including,
• a vertical stack including a source layer, a body layer, and a drain layer,
• the drain layer being connected to the data word line, and
• the source layer being configured to function as a gate electrode for the read transistor, and
• a gate adjacent to the vertical stack.