US 8,941,172 B2Granted

Non-volatile memory device and method of manufacturing the same

AssigneeSK hynix Inc.

InventorHyun Seung Yoo

Life of this patent

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Abstract

A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.

Claims11

Dependent claims

A non-volatile memory device, comprising:

a first vertical channel layer and a second vertical channel layer, both of which, generally protrude upwardly from a semiconductor substrate substantially in parallel;
a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates;
a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates;
a pipe channel layer above the semiconductor substrate and configured to couple the first vertical channel layer and the second vertical channel layer;
and
stack layers formed along outer walls of the first vertical channel layer, the second vertical channel layer and the pipe channel layer,
wherein the pipe channel layer includes an extension part passing through the stack layers and coupled to the semiconductor substrate.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/541,873Filed 5 Jul 2012
Priority: KR 10-2011-00668046 Jul 2011
Published: US 2013/0009235 A110 Jan 2013
Granted: 27 Jan 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 30/693
IGFETs having charge trapping gate insulators, e.g. MNOS transistors: vertical IGFETs having charge trapping gate insulators