Multiple patterning method

An integrated circuit memory comprising:

• a set of lines each having parallel X direction line portions in a first region and Y direction line portions in a second region, the second region offset from the first region;
• the lengths of the X direction line portions being substantially longer than the lengths of the Y direction line portions;
• the X direction and Y direction line portions having respective first and second pitches with the second pitch being at least 3 times larger than the first pitch;
• the Y direction line portions and the X direction line portions defining a set of nested ring-like lines including outer lines substantially encircling inner lines;
• and
• contact pickup areas at the Y direction line portions;
• the nested ring-like parallel lines comprising first and second ring-like parallel lines with opposed L-shaped segments with gaps along the Y direction line portions, the first and second ring-like parallel lines being adjacent to one another;
• the X direction line portions having first and second ends;
• the first ring-like parallel line comprising first and second X direction line portions and first and second Y direction line portions, each X direction line portion having first and second ends, the first Y direction line portion being at the first end of the first X direction line portion, the second Y direction line portion being at the second end of the second X direction line portion;
• and
• the second ring-like parallel line comprising third and fourth X direction line portions and third and fourth Y direction line portions, each of the third and fourth X direction line portions having first and second ends, the third Y direction line portion being at the second end of the third X direction line portion, the fourth Y direction line portion being at the first end of the fourth X direction line portion.