DRAM device
AssigneeRenesas Electronics Corporation
InventorsIchirou Mizuguchi, Hiroshi Furuta
Life of this patent
Estimating the term…
Abstract
A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P+ diffusion layer formed extending in the direction that the plurality of word lines extend and supplied with a p well voltage potential.
Claims14
A DRAM device comprising:
- a plurality of second conduction type MIS transistors arranged in a matrix shape over a first conduction type well;
- a plurality of capacitors formed corresponding to each of the plurality of second conduction type MIS transistors;
- a plurality of word lines formed corresponding to each row of the plurality of second conduction type MIS transistors;
- a plurality of bit lines formed to correspond to each column of the plurality of second conduction type MIS transistors;
- and
- a first conduction type first well voltage diffusion layer supplied with a well voltage potential, and formed extending in a direction that the plurality of word lines extend.
The DRAM device according to claim I, further comprising:
- a first and a second dummy word line supplied with the well voltage potential and formed between adjacent first and second word lines among the plurality of word lines,
- wherein the first conduction type first well voltage diffusion layer is formed between the first and the second dummy word lines.
The DRAM device according to claim I,
- wherein the first conduction type first well voltage diffusion layer is subjected to silicide treatment.
Dependencies are inferred from the claim text.