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US 8,941,153 B2Granted
FinFETs with different fin heights
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
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Abstract
An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
Claims18
An integrated circuit structure comprising:
- a semiconductor substrate;
- and
- a first FinFET comprising:
- a first shallow trench isolation (STI) region in the semiconductor substrate;
- a first semiconductor fin adjoining the first STI region and above a top surface of the first STI region, the first semiconductor fin having a first fin height from the top surface of the first STI region to a top surface of the first semiconductor fin;
- a first gate dielectric on the top surface and sidewalls of the first semiconductor fin;
- and
- a first gate electrode on the first gate dielectric;
- and
- a second FinFET comprising:
- a second STI region in the semiconductor substrate, bottom surfaces of the first STI region and the second STI region being level with each other;
- a second semiconductor fin adjoining the second STI region and above a top surface of the first STI region, the second semiconductor fin having a second fin height from the top surface of the second STI region to a top surface of the second semiconductor fin, the second fin height being less than the first fin height, the second semiconductor fin being a different fin than the first semiconductor fin;
- a second gate dielectric on a top surface and sidewalls of the second semiconductor fin;
- and
- a second gate electrode on the second gate dielectric, wherein the first FinFET is a p-type FinFET, and the second FinFET is an n-type FinFET, wherein a portion of the semiconductor substrate is laterally between the first FinFET and the second FinFET, and wherein the top surfaces of the first semiconductor fin, the second semiconductor fin, and the portion of the semiconductor substrate are level with each other.
12 more elements
A method of forming an integrated circuit structure, the method comprising:
- providing a semiconductor substrate comprising a first portion in a first device region, a second portion in a second device region, and a third portion laterally between the first portion and the second portion;
- forming a first shallow trench isolation (STI) region and a second STI region in the semiconductor substrate, wherein the first STI region is in the first device region, and the second STI region is in the second device region, and wherein the first STI region has a bottom surface level with a bottom surface of the second STI region;
- forming a p-type FinFET in the first device region comprising forming a first semiconductor fin over the semiconductor substrate and having a first fin height;
- and
- forming an n-type FinFET in the second device region comprising forming a second semiconductor fin over the semiconductor substrate and having a second fin height, wherein the first fin height is greater than the second fin height, the third portion of the semiconductor substrate having a top surface level with a top surface of the first semiconductor fin and with a top surface of the second semiconductor fin.
2 more elements
An integrated circuit structure comprising:
- a semiconductor substrate comprising a first portion in a first device region, and a second portion in a second device region;
- a first semiconductor fin over the semiconductor substrate and having a first fin height;
- a second semiconductor fin over the semiconductor substrate and having a second fin height, the first fin height being greater than the second fin height;
- a first portion of the semiconductor substrate between the first semiconductor fin and the second semiconductor fin, top surfaces of the first semiconductor fin, the second semiconductor fin, and the first portion of the semiconductor substrate being level with each other;
- a first shallow trench isolation (STI) region and a second STI region on opposite sides of the first semiconductor fin, the first STI region and the second STI region having first top surfaces level with a bottom of the first semiconductor fin;
- and
- a third STI region and a fourth STI region on opposite sides of the second semiconductor fin, the third STI region and the fourth STI region having second top surfaces level with a bottom of the second semiconductor fin, the first top surfaces being lower than the second top surfaces, the first STI region, the second STI region, the third STI region, and the fourth STI region having bottom surfaces level with each other.
4 more elements
Dependencies are inferred from the claim text.