US 8,941,152 B1 · Semiconductor device

Abstract

A method of forming a semiconductor device comprises forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package into a first chip package, a second chip package, and a third chip package. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.

Claims20

Dependent claims

A method of forming a semiconductor device comprising:

forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion;
forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion;
eutectic bonding the capping wafer and the base wafer to form a wafer package;
dicing the wafer package to separate the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation, the first chip package comprising the first chip package portion, the second chip package comprising the second chip package portion, and the third chip package comprising the third chip package portion;
and
placing the first chip package, the second chip package, and the third chip package onto a substrate.

3 more elements

A semiconductor device comprising:

a first chip package configured to perform a first operation, the first chip package comprising a first chip package portion comprising:
a first base wafer portion of a base wafer;
and
a first capping wafer portion of a capping wafer, the first capping wafer portion being eutectic bonded to the first base wafer portion;
a second chip package configured to perform a second operation, the second chip package comprising a second chip package portion comprising:
a second base wafer portion of the base wafer;
and
a second capping wafer portion of the capping wafer, the second capping wafer portion being eutectic bonded to the second base wafer portion;
a third chip package configured to perform a third operation, the third chip package comprising a third chip package portion comprising;
a third base wafer portion of the base wafer;
and
a third capping wafer portion of the capping wafer, the third capping wafer portion being eutectic bonded to the third base wafer portion;
and
a CMOS chip package,
wherein
the CMOS chip package, the first chip package, the second chip package and the third chip package are bonded together by a molding compound, and
the first chip package, the second chip package and the third chip package are separate components derived from the capping wafer and the base wafer.

14 more elements

A semiconductor device comprising:

a first chip package configured to perform a first operation, the first chip package comprising a first chip package portion comprising a first base wafer portion of a base wafer and a first capping wafer portion of a capping wafer eutectic bonded to the first base wafer portion;
a second chip package configured to perform a second operation, the second chip package comprising a second chip package portion comprising a second base wafer portion of the base wafer and a second capping wafer portion of the capping wafer eutectic bonded to the second base wafer portion;
a third chip package configured to perform a third operation, the third chip package comprising a third chip package portion comprising a third base wafer portion of the base wafer and a third capping wafer portion of the capping wafer eutectic bonded to the third base wafer portion;
a CMOS chip package;
a plurality of communication openings in the capping wafer, the plurality of communication openings comprising a first pair of communication openings configured to substantially align with the first chip package portion, a second pair of communication openings configured to substantially align with the second chip package portion, and a third pair of communication openings configured to substantially align with the third chip package portion;
an oxidation layer in the plurality of communication openings;
a dielectric material in the plurality of communication openings;
and
a plurality of isolation trenches between the pairs of communication openings,
wherein
the CMOS chip package, the first chip package, the second chip package and the third chip package are bonded together by a molding compound, and
the first chip package, the second chip package and the third chip package are separate components derived from the capping wafer and the base wafer.

9 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims20