Power routing in standard cells
AssigneeSynopsys, Inc.
InventorsDeepak D. Sherlekar, Vahe Hovsepyan
Life of this patent
Estimating the term…
Abstract
An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules.
Claims20
A non-transitory computer readable medium storing a cell library, the cell library including at least one cell that comprises:
- a first power pin extending along a first boundary of the cell for carrying a first power supply voltage;
- a second power pin extending along an interior of the cell for carrying a second power supply voltage;
- and
- a first cell pin for carrying one of an input signal or output signal of the cell and located between the second power pin and a second boundary of the cell that is opposite from the first boundary.
A computer implemented method for cell based layout generation, the method comprising:
- receiving a plurality of cells, at least one of the cells comprising:
- a first power pin extending along a first boundary of the cell for carrying a first power supply voltage;
- a second power pin extending along an interior of the cell for carrying a second power supply voltage;
- and
- a first cell pin for carrying one of an input signal or output signal of the cell and located between the second metal wire and a second boundary of the cell that is opposite from the first boundary;
- and
- generating a layout for an integrated circuit based on the plurality of cells.
A non-transitory computer readable medium configured to store instructions for cell based layout generation, the instructions when executed by a processor cause the processor to perform steps comprising:
- receiving a plurality of cells, at least one of the cells comprising:
- a first power pin extending along a first boundary of the cell for carrying a first power supply voltage;
- a second power pin extending along an interior of the cell for carrying a second power supply voltage;
- and
- a first cell pin for carrying one of an input signal or output signal of the cell and located between the second metal wire and a second boundary of the cell that is opposite from the first boundary;
- and
- generating a layout for an integrated circuit based on the plurality of cells.
Dependencies are inferred from the claim text.