Normally-off III-nitride transistors with high threshold-voltage and low on-resistance

A III-nitride transistor comprising:

• a III-nitride channel layer;
• a barrier layer over the channel layer;
• a dielectric layer on top of the barrier layer;
• a source electrode contacting the channel layer;
• a drain electrode contacting the channel layer;
• a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer;
• a gate insulator lining the gate trench and extending over the dielectric layer, the gate insulator comprising a single-crystalline AlN layer at the bottom of the gate trench, a polycrystalline AlN layer on the single crystalline AlN layer, and an insulating layer comprising AL2O3, AlON, or SiN on the polycrystalline AlN layer;
• and
• a gate electrode in the gate trench and extending partially toward the source electrode and the drain electrode to form an integrated gate field-plate.

A method of fabricating a III-nitride transistor comprising:

• forming a III-nitride channel layer;
• forming a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers;
• forming a dielectric layer on top of the barrier layer;
• forming a source electrode contacting the channel layer;
• forming a drain electrode contacting the channel layer;
• forming a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer so that a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nanometers and less than or equal to 5 nanometers;
• forming a gate insulator lining the gate trench and extending over the dielectric layer;
• and
• forming a gate electrode in the gate trench and extending partially toward the source electrode and the drain electrode to form an integrated gate field-plate.

A method of fabricating a III-nitride transistor comprising:

• forming a III-nitride channel layer;
• forming a barrier layer over the channel layer;
• forming a dielectric layer on top of the barrier layer;
• forming a source electrode contacting the channel layer;
• forming a drain electrode contacting the channel layer;
• forming a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer;
• forming a gate insulator lining the gate trench and extending over the dielectric layer, the gate insulator comprising a single-crystalline AlN layer at the bottom of the gate trench, a polycrystalline AlN layer on the single crystalline AlN layer, and an insulating layer comprising AL2O3, AlON, or SiN on the polycrystalline AlN layer;
• and
• forming a gate electrode in the gate trench and extending partially toward the source electrode and the drain electrode to form an integrated gate field-plate.