Method to perform electrical testing and assembly of electronic devices

A method, comprising:

• performing electrical wafer testing and assembly of a first electronic device on a wafer, the first electronic device including an insulating layer on the wafer, a passivation layer covering the insulating layer, and a first pad made in the insulating layer, the performing including:
• providing said first electronic device with an extended metallization layer extending said passivation layer from said first pad to the non-active area of said wafer;
• connecting said first electronic device to a testing apparatus;
• performing the electrical wafer testing of said first electronic device by positioning a probe of said testing apparatus on a portion of said extended metallization layer positioned on said non-active area;
• cutting said wafer after performing the electrical wafer testing of said first electronic device, the cutting including reducing an extension of said metallization layer to an edge of said first electronic device;
• forming on said extended metallization layer an electrical connection after cutting said wafer;
• and
• forming a through-silicon via in said first electronic device, and in contact with said extended metallization layer, forming the through-silicon via including depositing a layer of metallic material that extends from said first pad vertically through at least part of said first electronic device, wherein said extended metallization layer is formed simultaneously with forming the layer of metallic material.

A method to perform electrical testing and assembly of a first electronic device comprised in a wafer and including a first pad in an active area of the first electronic device, said pad being surrounded by a dielectric layer which is covered by a passivation layer, the method comprising:

• forming a non-active area of the wafer with a lowered surface with respect to a surface of said first electronic device;
• electrically coupling said electronic device to a testing apparatus;
• providing said first electronic device with an extended metallization layer extending on said passivation layer from said first pad to the non-active area of said wafer, said non-active area being free of pads;
• performing the electrical testing of said electronic device, the performing including positioning a probe of said testing apparatus on a portion of said extended metallization layer on said non-active area, no pads having been realized on said non-active region under said portion;
• cutting said wafer, the cutting including reducing an extension of said extended metallization layer to an edge of said first electronic device;
• and
• embedding said first electronic device inside a package and forming on said extended metallization layer an electric connection configured to be connected to a circuit in said package.

A method to perform electrical testing and assembly of a first electronic device comprised in a wafer and including a first pad in an active area of the first electronic device, said pad being surrounded by dielectric layer which is covered by a passivation layer, the method comprising:

• forming a non-active area of the wafer with a lowered surface with respect to a surface of said first electronic device;
• electrically coupling said electronic device to a testing apparatus;
• providing said first electronic device with an extended metallization layer extending on said passivation layer from said first pad to the non-active area of said wafer, said non-active area being free of pads;
• performing the electrical testing of said electronic device, the performing including positioning a probe of said testing apparatus on a portion of said extended metallization layer on said non-active area, no pads having been realized on said non-active region under said portion;
• cutting said wafer, the cutting including reducing an extension of said extended metallization layer to an edge of said first electronic device;
• embedding said first electronic device inside a package and forming on said extended metallization layer an electric connection configured to be connected to a circuit in said package;
• and
• forming a through-silicon via in said first electronic device, and in contact with said extended metallization layer, forming the through-silicon via including depositing a layer of metallic material that extends from said first pad vertically through at least part of said first electronic device, wherein said extended metallization layer is formed simultaneously with forming the layer of metallic material.