Uncooled infrared detector and methods for manufacturing the same

An infrared detector manufactured from a foundry-defined silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) wafer, the infrared detector comprising:

• a plurality of walls forming a through well defining a first opening and a second opening opposing the first opening;
• an infrared sensor configured to detect an infrared wave passing through one of the first opening or the second opening of the through well;
• and
• a support arm connecting the sensor to at least one of the plurality of walls so as to suspend the infrared sensor within the through well and adjacent to the first opening.

A method for manufacturing an uncooled infrared detector from a foundry-defined silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) wafer having a substrate layer, an insulation layer formed on the substrate layer and having a pixel region and a wall region surrounding the pixel region, a pixel structure formed on the pixel region of the insulation layer, a wall structure formed adjacent to the pixel structure and on the wall region of the insulation layer, a dielectric layer covering the pixel structure and the wall structure, a pixel mask formed within the dielectric layer and covering the pixel structure, and a wall mask formed within the dielectric layer and covering the wall structure, the method comprising the steps of:

• performing a first vertical etching through a portion of the substrate layer to define a back pixel space terminated by the pixel region of the insulation layer;
• performing a second vertical etching through a portion of the dielectric layer not covered by the pixel mask and the wall mask and through a portion of the insulation layer not covered by the pixel mask and the wall mask, so as to define a front pixel space for separating the pixel structure from the wall structure;
• and
• removing the pixel mask and the wall mask.

A method for manufacturing an uncooled infrared detector from a foundry-defined silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) wafer having a substrate layer, an insulation layer formed on the substrate layer and having a pixel region and a wall region surrounding the pixel region, a pixel structure formed on the pixel region of the insulation layer, a wall structure formed adjacent to the pixel structure and on the wall region of the insulation layer, a dielectric layer covering the pixel structure and the wall structure, a pixel mask formed within the dielectric layer and covering the pixel structure, and a wall mask formed within the dielectric layer and covering the wall structure, the method comprising the steps of:

• performing a vertical etching through a portion of the dielectric layer not covered by the pixel mask and the wall mask and through a portion of the insulation layer not covered by the pixel mask and the wall mask, so as to define a front pixel space for separating the pixel structure from the wall structure;
• removing the pixel mask and the wall mask;
• and
• performing an anisotropic silicon etching to form a well on the substrate layer and under the pixel structure, the well defining a back pixel space joining the front pixel space for thermally isolating the pixel structure from the substrate layer and the wall structure.