Solid-state imaging apparatus
AssigneeRenesas Electronics Corporation
InventorsShunsuke Okura, Koji Shida, Hiroshi Kato
Life of this patent
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Abstract
There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.
Claims10
A solid-state imaging apparatus comprising:
- a pixel circuit to output an analog voltage having a level corresponding to an incident light quantity;
- a reference voltage generation circuit to generate a reference voltage whose voltage value linearly varies with the time;
- a counter to generate a counter code whose count value linearly varies with the time at a predetermined cycle;
- and
- an integral A/D converter to convert the analog voltage into a digital signal based on the reference voltage and the counter code,
- wherein the integral A/D converter includes:
- a comparator to compare the reference voltage with the analog voltage in terms of high and low states;
- and
- a latch circuit to latch the counter code based on a comparison result from the comparator when high-low relationship between the reference voltage and the analog voltage reverses, and
- wherein the counter code includes:
- a low-order bit code including as many as N clock signals (N is an integer greater than or equal to 2) that have equal frequencies and allow phases to shift from each other by the predetermined cycle;
- and
- a high-order bit code including a gray code whose count value varies at a cycle equal to the predetermined cycle multiplied by M (M is an integer greater than N).
A solid-state imaging apparatus comprising:
- a plurality of pixel circuits that are provided for a plurality of rows and columns and each output an analog voltage having a level corresponding to an incident light quantity;
- a row scanning circuit that successively selects the rows one by one and activates each pixel circuit for a selected row;
- a signal line that is provided correspondingly to each of the columns and is coupled to each pixel circuit for a corresponding column;
- a reference voltage generation circuit that generates a reference voltage whose voltage value linearly varies with a lapse of time;
- a counter that generates a counter code whose count value linearly varies with the time at a predetermined cycle;
- and
- an integral A/D converter that is provided correspondingly to each signal line and converts the analog voltage into a digital signal based on the reference voltage and the counter code when the analog voltage is output to a corresponding signal line from a corresponding pixel circuit activated by the row scanning circuit,
- wherein the integral A/D converter includes:
- a comparator to compare the reference voltage with the analog voltage in terms of high and low states;
- and
- a latch circuit to latch the counter code based on a comparison result from the comparator when high-low relationship between the reference voltage and the analog voltage reverses, and
- wherein the counter code includes:
- a low-order bit code including as many as N clock signals (N is an integer greater than or equal to 2) that have equal frequencies and allow phases to shift from each other by the predetermined cycle;
- and
- a high-order bit code including a gray code whose count value varies at a cycle equal to the predetermined cycle multiplied by M (M is an integer greater than N).
Dependencies are inferred from the claim text.