Radical oxidation process for fabricating a nonvolatile charge trap memory device

A method of fabricating a memory device, comprising:

• subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in the substrate, wherein the channel comprises polysilicon;
• forming a multi-layer charge storing layer overlying the tunnel oxide layer, the multi-layer charge storing layer comprising a first layer comprising a nitride closer to the tunnel oxide layer, and a second layer comprising a nitride, wherein the first layer is separated from the second layer by an anti-tunneling layer comprising an oxide;
• and
• subjecting the substrate to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer.

A method of fabricating a memory device, comprising:

• forming on a surface of a substrate a stack of layers including at least a first dielectric layer, a gate layer and a second dielectric layer, wherein the gate layer is separated from the surface of the substrate by the first dielectric layer and the second dielectric layer is separated from the first dielectric layer by the gate layer;
• forming an opening extending through the stack of layers to a first doped diffusion region formed on the surface of the substrate;
• forming on sidewalls of the opening a high-temperature-oxide (HTO) layer;
• forming on an inside sidewall of the HTO layer a multi-layer charge storing layer, the multi-layer charge storing layer comprising an oxygen-lean, first oxynitride layer on the HTO layer in which a stoichiometric composition of the first oxynitride layer results in it being trap dense, and an oxygen-rich, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free;
• forming on an inside sidewall of the multi-layer charge storing layer a tunnel oxide layer;
• and
• forming on an inside sidewall of the tunnel oxide layer a vertical channel comprising polysilicon,
• wherein the vertical channel electrically couples first doped diffusion region to a second doped diffusion region formed in a layer of semiconducting material subsequently formed over the stack of layers and the opening.