Double patterning strategy for contact hole and trench in photolithography

#The present disclosure is related to the following commonly-assigned U.S. Provisional Patent Application, the entire disclosure of which is incorporated herein by reference: U.S. Provisional Application No. 61/245,447; for “Double Patterning Strategy for Contact Hole and Trench in Photolithography”.

#Semiconductor technologies are continually progressing to smaller feature sizes, for example down to feature sizes of 65 nanometers, 45 nanometers, and below. A patterned photoresist (resist) layer used to produce such small feature sizes typically has a high aspect ratio. Maintaining a desired critical dimension (CD) can be very difficult for various reasons, especially for a resist layer with a high aspect ratio. The double patterning processes have been introduced to form various features with smaller dimensions. However, conventional double patterning processes involve multiple etching processes with high manufacturing cost and low throughput.

#Aspects of the present disclosure are best understood from the following detailed description when read in association with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features in the drawings are not drawn to scale. In fact, the dimensions of illustrated features may be arbitrarily increased or decreased for clarity of discussion.

#FIGS. 1 through 9 are sectional views of one embodiment of a semiconductor device during various fabrication stages.

#FIG. 10 is a flowchart showing one embodiment of a lithography patterning method.

#It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

#Referring to FIGS. 1 and 10, the method 200 may begin at step 202 by forming one or more underlying material layer (also referred to as an “under-material” layer) on a substrate 110. The substrate 110 may be made of silicon, some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Alternatively, the substrate 110 may include a non-semiconductor material such as a glass for thin-film-transistor liquid crystal display (TFT-LCD) devices, or fused quartz or calcium fluoride for a photomask (mask). The substrate 110 may include various doped regions, dielectric features, and multilevel interconnects. In one embodiment, the substrate 110 includes various doped features for various microelectronic components, such as a complementary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, memory cell, and/or capacitive element. In another embodiment, the substrate 110 includes conductive material features and dielectric material features configured for coupling and isolating various microelectronic components, respectively. In another embodiment, the substrate 110 includes one or more material layers formed thereon.

#The under-material layer may be a single material or layers of different materials. In the embodiment shown in FIGS. 1-10, a material layer 112 is formed on the substrate 110. The material layer 112, in one embodiment, may be a dielectric material used for ILD or IMD including silicon oxide and low-k dielectric materials with a dielectric constant less than about 4. The material layer 112, in another embodiment, may be a silicon, polysilicon, metal materials or combinations thereof used for electrode gate. In the present embodiment, the material layer 112 is a low-k dielectric layer. Suitable low-k dielectric materials include fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond®. (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other proper porous polymeric materials. The dielectric material may be formed by a suitable process including spin-on coating or chemical vapor deposition (CVD). The material layer 112, for example, may have a thickness ranging from about 500 angstroms to about 5000 angstroms.