US 8,940,640 B2 · Source/drain structure of semiconductor device

Abstract

The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.

Claims20

Dependent claims

A method for fabricating a field effect transistor comprising:

providing a substrate comprising a major surface;
forming a shallow trench isolation (STI) region within the substrate;
forming a gate stack adjacent to the STI region on the major surface of the substrate;
forming a spacer adjoining at least one side of the gate stack;
recessing the substrate to form a source/drain (S/D) recess adjacent to the spacer;
exposing a surface of the S/D recess to a vapor mixture comprising XeF2, NH3 and H2 at a first temperature;
ceasing to expose the surface of the S/D recess to the vapor mixture;
after the step of ceasing to expose the surface of the S/D recess to the vapor mixture, heating the substrate to a second higher temperature to form a S/D cavity extending below the spacer;
selectively growing a S/D extension partially filling in the S/D cavity;
and
selectively growing a strained material filling in the S/D cavity.

8 more elements

A method for fabricating a field effect transistor comprising:

forming a fin extending from a major surface of a substrate;
forming a dielectric layer surrounding the fin;
recessing a top surface of the dielectric layer so that the top surface of the fin extends above the top surface of the dielectric layer;
forming a patterned gate stack extending over a portion of the top surface of the fin and extending along sidewalls of the fin, the gate stack extending laterally in a first direction and the fin extending laterally in a second direction orthogonal to the first direction;
forming a spacer adjacent at least one sidewall of the gate stack;
using the gate stack and the spacer as a mask, recessing a portion of the fin to form a source/drain (S/D) recess adjacent the spacer, the S/D recess having a recess sidewall and a recess bottom;
vapor phase etching the recess sidewall and the recess bottom by exposing the recess sidewall and the recess bottom to a vapor mixture comprising XeF2, NH3 and H2 at a first temperature;
ceasing the vapor phase etching;
after ceasing the vapor phase etching, extending the S/D recess under the spacer by heating the substrate to a second higher temperature;
selectively growing a S/D extension on the recess sidewall and the recess bottom;
and
selectively growing a strained material on the S/D extension and filling the S/D recess.

9 more elements

Dependencies are inferred from the claim text.

Source/drain structure of semiconductor device

Life of this patent

Source/drain structure of semiconductor device

Life of this patent

Abstract

Claims20