Substrate wiring method and semiconductor manufacturing device
AssigneesTokyo Electron Limited, Iwatani Corporation
InventorsSatohiko Hoshino, Hidefumi Matsui, Masaki Narushima
Life of this patent
Estimating the term…
Abstract
In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.
Claims12
A substrate wiring method for wiring a substrate on which a wiring pattern is formed in a processing chamber maintained in a vacuum state, comprising:
- a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas;
- and
- an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas,
- wherein the embedding step includes forming a barrier material of metal by embedding the metal nanoparticles in a surface of the wiring pattern, and embedding a wiring metal in the wiring pattern in which the barrier material is formed, and
- wherein in the embedding step, the clustered metal gas is formed by ejecting a metal source into the processing chamber from a gas nozzle whose internal pressure PS is maintained to be higher than an internal pressure P0 of the processing chamber.
A substrate wiring method for wiring a substrate on which a wiring pattern is formed in a processing chamber maintained in a vacuum state, comprising:
- a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas;
- and
- an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas,
- wherein the embedding step includes forming a barrier material of metal by embedding the metal nanoparticles in a surface of the wiring pattern, and embedding a wiring metal in the wiring pattern in which the barrier material is formed,
- wherein a distance d between the gas nozzle and the substrate is set to be longer than a distance Xm from an outlet of the gas nozzle to a position where a shock wave is generated, which is defined in the following Eq. 1:
- X
- m
- D
- O
- =
- 0.67
- ×
- (
- P
- O
- P
- S
- )
- 1
- 2
- Eq
- .
-
- 1
- where D0 is an inner diameter of the outlet of the gas nozzle, PS is an inner pressure of the gas nozzle, and P0 is an inner pressure of the processing chamber, and
- wherein the barrier material is formed by allowing the metal nanoparticles to collide with the substrate by using the generated shock wave.
A semiconductor manufacturing device for wiring a substrate on which a wiring pattern is formed in a processing chamber maintained in a vacuum state, comprising:
- a gas nozzle whose internal pressure PS is maintained to be higher than an internal pressure P0 of the processing chamber,
- wherein the semiconductor manufacturing device performs a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas;
- and
- an embedding step in which, after the preprocessing step, a clustered metal gas is generated by ejecting a metal source into the processing chamber from the gas nozzle and metal nanoparticles are embedded in the wiring pattern using a clustered metal gas, and
- wherein the semiconductor manufacturing device performs, in the embedding step, forming a barrier material of metal by embedding the metal nanoparticles in a surface of the wiring pattern, and embedding a wiring metal in the wiring pattern in which the barrier material is formed.
Dependencies are inferred from the claim text.