Method of fabricating a high-voltage transistor with an extended drain structure

A method for fabricating a power transistor comprising:

• forming an epitaxial layer of a first conductivity type on a substrate, the epitaxial layer being formed with a linearly graded doping profile;
• forming first and second trenches in the epitaxial layer that defines a mesa, the mesa having first and second sidewalls;
• covering the first and second sidewalls with a dielectric material;
• forming first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from a top surface of the semiconductor substrate down to near a bottom of the mesa;
• forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the bottom of the mesa;
• and
• forming a trench gate within the dielectric material adjacent the body region, the trench gate being insulated from the body region and the first and second field plates.