Nonvolatile memory comprising mini wells at a floating potential

#1. Technical Field

#The present disclosure relates to nonvolatile memories in integrated circuits on semiconductor chips. More particularly, the present disclosure relates to memories comprising memory cells with programming and erasure by tunneling, called Uniform Channel Program or UCP memory cells. More particularly, the present disclosure relates to UCP memory cells with two transistors, comprising a selection transistor and a charge accumulation transistor, such as a floating gate transistor.

#2. Description of the Related Art

#Embodiments of a method of reading memory cells, memory cells structures, and memory structures according to the disclosure will be described in the following in a non-limiting manner, in relation with the appended drawings in which:

#FIG. 1, previously described, is a schematic cross-sectional view of two conventional memory cells,

#FIG. 2, previously described, is the electric diagram of the memory cells,

#In relation with FIG. 4, table RD2 in Annex describes a method according to one embodiment of the disclosure of reading the memory cells C11, C12 shown in FIG. 1. The voltages listed in the first column of the table were previously described in relation with the table REF1. The example described here relates to the read of the memory cell C11. The cell C12 may be read in a similar manner by applying to it the voltages applied to the cell C11, and vice-versa.

#The read method produces an effect similar to that described by the table RD 1: the cell C11 is conducting and is traversed by a current that also traverses the bitline BL. This current is sensed by a sense amplifier (not shown).

#This method differs from that described by the table RD1 in that the gates of the two selection transistors ST11 and ST12 receive the selection voltage during read Von, the non-selection voltage during read Voff no longer being used for the considered pair of memory cells. Thus, the selection transistor ST12 of the cell C12 is set in the conducting state and has a conductive channel in its channel region CH2. To prevent a current from flowing through the non-selected cell C12, the voltage CGV applied to the control gate of the transistor FGT12, instead of being equal to the non-read voltage Vnread, is equal to an inhibition voltage Vinh, which forces the transistor FGT12 into the blocked state and prevents it from conducting. The inhibition voltage Vinh, here negative, is chosen to be less than the lowest possible value of the threshold voltage of the transistor FGT12 in order to ensure that the transistor FGT12 remains in the blocked state. The threshold voltage is a function of the state of the transistor, programmed or erased. In other words, the selection transistor ST12, usually used for the selection for read of a memory cell, is no longer used for its usual function for the pair of memory cells considered, and the floating gate transistor FGT12 is forced into the blocked state.