Scaled equivalent oxide thickness for field effect transistor devices
AssigneeInternational Business Machines Corporation
InventorsTakashi Ando, Changhwan Choi, Unoh Kwon, Vijay Narayanan
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Abstract
A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.
Claims12
A method of forming field effect transistor (FET) device, the method comprising:
- forming a first gate stack portion and a second gate stack portion on a substrate;
- the first gate stack portion further comprising a first interfacial (IL) layer formed on the substrate, a dielectric layer formed on the first IL layer, a stoichiometric TiN layer formed over the dielectric layer, and a capping layer formed over the stoichiometric TiN layer;
- and
- the second gate stack portion further comprising a second IL layer formed on the substrate, the dielectric layer formed on the second IL layer, the stoichiometric TiN layer formed over the dielectric layer, and the capping layer formed over the stoichiometric TiN layer, wherein forming the second gate stack portion further comprises:
- forming a first Ti-rich TiN layer on the dielectric layer;
- forming a metallic layer on the first Ti-rich TiN layer;
- forming a second Ti-rich TiN layer on the metallic layer;
- and
- forming the stoichiometric TiN layer on the second Ti-rich TiN layer;
- wherein the second IL layer has a reduced oxygen content and an increased silicon content with respect to the first IL layer such that an equivalent oxide thickness (EOT) of the second gate stack portion is reduced with respect to the first gate stack portion.
A method of forming a field effect transistor (FET) device, the method comprising:
- forming a first gate stack portion and a second gate stack portion on a substrate;
- the first gate stack portion further comprising a first SiO2 interfacial (IL) layer formed on the substrate, a dielectric layer formed on the first SiO2 IL layer, a stoichiometric TiN layer formed over the dielectric layer, and a capping layer formed over the stoichiometric TiN layer;
- and
- the second gate stack portion further comprising a second SiO2 IL layer formed on the substrate, the dielectric layer formed on the second SiO2 IL layer, the stoichiometric TiN layer formed over the dielectric layer, and the capping layer formed over the stoichiometric TiN layer, wherein forming the second gate stack portion further comprises:
- forming a first Ti-rich TiN layer formed on the dielectric layer;
- forming a metallic layer on the first Ti-rich TiN layer;
- forming a second Ti-rich TiN layer on the metallic layer;
- and
- forming the stoichiometric TiN layer on the second Ti-rich TiN layer;
- forming a drain region disposed between the first gate stack portion and the second gate stack portion;
- forming a first source region disposed adjacent to the second gate stack portion;
- and
- forming a second source region disposed adjacent to the second gate stack portion;
- wherein the second SiO2 IL layer has a reduced oxygen content and an increased silicon content with respect to the first SiO2 IL layer due to removal of O2 therefrom such that an equivalent oxide thickness (EOT) of the second gate stack portion is reduced with respect to the first gate stack portion.
Dependencies are inferred from the claim text.