Low temperature coefficient resistor in CMOS flow

A process of forming an integrated circuit, comprising the steps:

• providing a substrate;
• forming an NMOS gate dielectric layer on said substrate;
• forming a PMOS gate dielectric layer on said substrate;
• forming a gate polysilicon layer over said substrate, said NMOS gate dielectric layer and said PMOS gate dielectric layer;
• forming a pregate etch implant mask on said gate polysilicon layer
• performing an pregate etch implant operation which implants an n-type dopant plus carbon into said gate polysilicon layer;
• forming a gate mask on said gate polysilicon layer;
• etching said gate polysilicon layer to form:
• an NMOS gate on said NMOS gate dielectric layer;
• a PMOS gate on said PMOS gate dielectric layer;
• and
• a resistor layer, said resistor layer having a body region and having head regions at each end of said body region;
• forming an NLDD implant mask over said substrate which:
• exposes said NMOS gate and said substrate adjacent to said NMOS gate;
• and
• covers said PMOS gate and said substrate adjacent to said PMOS gate;
• performing an NLDD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NLDD layers;
• forming sidewall spacers adjacent both said NMOS gate and said PMOS gate;
• forming an NSD implant mask over said substrate which:
• exposes said NMOS gate and said substrate adjacent to said NMOS gate;
• and
• covers said PMOS gate and said substrate adjacent to said PMOS gate;
• performing an NSD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NSD layers;
• forming a PSD implant mask over said substrate which:
• exposes said PMOS gate and said substrate adjacent to said PMOS gate;
• and
• covers said NMOS gate and said substrate adjacent to said NMOS gate
• performing a PSD implant operation which implants p-type dopants into said substrate adjacent to said PMOS gate to form PSD layers;
• performing at least one of said NLDD and said NSD implant operations into said resistor layer;
• forming a resistor silicide block layer over said body region of said resistor layer where said silicide block layer is not formed of material of said sidewall spacers;
• forming metal silicide layers on said head regions of said resistor layer, on said NSD layers adjacent to said NMOS gate, and on said PSD layers adjacent to said PMOS gate;
• forming a PMD layer over said metal silicide layers and over said resistor silicide block layer;
• and
• forming contacts through said PMD layer, said contacts making electrical connection to said metal silicide layers on said NSD layers and to said silicide layers on said PSD layers.