Enhancement-mode GaN MOSFET with low leakage current and improved reliability
AssigneeTexas Instruments Incorporated
InventorJamal Ramdani
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AssigneeTexas Instruments Incorporated
InventorJamal Ramdani
Estimating the term…
An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
A method of forming a transistor comprising:
Dependencies are inferred from the claim text.
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Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
Manufacture or treatment: of FETs having insulated gates [IGFET]
Having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs: having wide bandgap…
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions
About 3 years 4 months of term left · ends 3 Mar 2030 (estimated)
1. Field of the Invention
The present invention relates to GaN MOSFETs and, more particularly, to an enhancement-mode MOSFET with low leakage current and improved reliability.
2. Description of the Related Art
FIGS. 1-4 are a series of cross-sectional views illustrating an example of a method of forming an enhancement-mode GaN MOSFET 100 in accordance with the present invention.
FIGS. 5-9 are a series of cross-sectional views illustrating an example of a method of forming an enhancement-mode GaN MOSFET 500 in accordance with an alternate embodiment of the present invention.
FIG. 10 is a band diagram illustrating the leakage current in accordance with the present invention.
FIGS. 1-4 show a series of cross-sectional views that illustrate an example of a method of forming an enhancement-mode GaN MOSFET 100 in accordance with the present invention. As described in greater detail below, the method of the present invention forms a SiO2/Si3N4 gate insulation layer on an AlGaN barrier layer (or optional InAlGaN barrier layer) which significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer. Reducing the density of interface states significantly reduces the number of trapping sites which, in turn, improves the long-term reliability on the GaN devices.
As shown in FIG. 1, the method of the present invention utilizes a conventionally-formed semiconductor substrate 110. Substrate 110 can be implemented as an insulating substrate or with a highly resistive material such as silicon (e.g., <111>), sapphire, or silicon carbide. As further shown in FIG. 1, the method of the present invention begins by forming an epitaxial layer 112 on substrate 110. Epitaxial layer 112, which is formed in a metal organic chemical vapor deposition (MOCVD) reactor using a conventional process, includes an undoped AlGaN buffer layer 114, an undoped GaN channel layer 116, and an undoped or n-doped AlGaN barrier layer 118 (or optionally an undoped or n-doped InAlGaN barrier layer 118). The AlGaN buffer layer 114, in turn, includes a number of undoped AlGaN layers with different aluminum compositions that are used to mitigate stress.
As shown in FIG. 2, in accordance with the present invention, after epitaxial layer 112 has been formed, a Si3N4 layer 120 is epitaxially grown on the AlGaN barrier layer 118 directly in the same MOCVD reactor as the AlGaN barrier layer 118 using SiH4 and NH3. In other words, the Si3N4 layer 120 is epitaxially grown after the AlGaN layer 118 is grown without removing the structure with the AlGaN layer 118 from the MOCVD reactor.