Bulk FinFET ESD devices
AssigneeInternational Business Machines Corporation
InventorsRobert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher Stephen Putnam
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Abstract
Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.
Claims10
A method of manufacturing a dual ESD protection device in fin field effect transistor (FinFET) process technology, the method comprising:
- providing a bulk silicon wafer substrate;
- forming a plurality of fins on a top portion of the bulk silicon wafer substrate;
- forming an oxide isolation region between each of the fins, the oxide isolation region including a shallow trench isolation (STI);
- performing a selective epitaxial growth process to merge a portion of the plurality of fins;
- and
- patterning, etching, and implanting the portion of the plurality of fins to form the dual ESD protection device including:
- a first ESD device positioned above the oxide isolation region;
- and a second ESD device positioned below the oxide isolation region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the oxide isolation region.
Dependencies are inferred from the claim text.