Dual-gate bio/chem sensor

A method of forming a semiconductor structure comprising:

• forming non-contiguous first conductivity type semiconductor regions within a semiconductor base layer of a semiconductor-on-insulator substrate, said semiconductor-on-insulator substrate further comprise at least one buried dielectric material layer having a first thickness located on a surface of the semiconductor base layer, and a semiconductor-on-insulator layer located on an uppermost surface of said at least one buried dielectric material layer;
• patterning said semiconductor-on-insulator layer forming an active device region;
• forming a transistor within said active device region, wherein said transistor comprises a gate dielectric material having a second thickness, wherein said second thickness of said gate dielectric material is less than said first thickness of said at least one buried dielectric material layer;
• forming an interconnect structure straddling said transistor located within said active device region;
• removing a portion of said semiconductor base layer of said semiconductor-on-insulator substrate stopping on a surface of each of said non-contiguous first conductivity type semiconductor regions and providing a cavity between the non-contiguous first conductivity type semiconductor regions that exposes a portion of the at least one buried dielectric material layer;
• and
• thinning the exposed portion of the at least one buried dielectric material layer to a third thickness which is less than the second thickness of the at least one gate dielectric material layer of the transistor.