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US 8,940,555 B2Granted
Method and system for determining overlap process windows in semiconductors by inspection techniques
AssigneeGlobalfoundries Inc.
InventorLothar Bauch
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Abstract
The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
Claims11
A method, comprising:
- transferring a first pattern of a first layout layer of a semiconductor device into a material layer formed above a first test region and a second test region of a substrate;
- transferring a second pattern of a second layout layer of said semiconductor device into said material layer formed above said first test region, said first and second layout layers being spatially correlated to each other so as to define an overlap area;
- transferring a geometrically modulated version of said second pattern into said material layer formed above said second test region;
- and
- determining a structural difference in said material layer between said first test region and said second test region so as to assess a process margin with respect to said overlap area.
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Dependencies are inferred from the claim text.