Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness

#The invention generally relates to the fabrication of semiconductor wafers and, more particularly, to a method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness.

#Complementary metal oxide semiconductor (CMOS) devices built on an extremely thin semiconductor-on-insulator (SOI) substrate has been one of the viable options for continued scaling of CMOS technology to 22 nm node and beyond. For viable use in the 22 nm node, ETSOI wafers require an extremely thin SOI layer having a thickness of about 60 Angstroms (Å) or less with a variation in the thickness of about +/−6 Å or less. The electrical characteristics of devices formed using ETSOI technology are influenced by the thickness of the ETSOI layer. For example, the threshold voltage (Vt) of a device formed using ETSOI is primarily determined by the thickness of the ETSOI layer. As such, any variation in the thickness of an ETSOI layer of wafer can lead to undesirable variations in threshold voltage. For example, when many chips are created from a 300 mm ETSOI wafer, variations in the thickness of the ETSOI layer can result in threshold voltage variation from chip to chip, or within a single chip.

#Wafer thinning is a known technique for creating an ETSOI wafer from an SOI wafer. However, conventional wafer thinning processes produce an ETSOI layer with too much within-a-wafer thickness variation for the desired 22 nm node. For example, a known wafer thinning technique is to oxidize a bonded or SIMOX (e.g., separated by ion implantation of oxygen) SOI wafer in a furnace and then wet etch the oxide. However, this method does not improve SOI layer thickness variation, but rather simply transfers any thickness variation that is initially present in the SOI layer to the ETSOI layer. For example, known oxidation-based wafer thinning techniques are capable of producing an ETSOI layer having a thickness of about 60 Å, but with a thickness variation of about +/−20 Å. As such, conventional wafer thinning techniques do not provide the ETSOI layer thickness uniformity required by the 22 nm node.

#The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

#FIG. 1 shows a semiconductor structure and process in accordance with aspects of the invention;

#FIG. 2 shows a topographical map of a semiconductor structure in accordance with aspects of the invention;

#The invention generally relates to the fabrication of semiconductor wafers and, more particularly, to a method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness. In accordance with aspects of the invention, the thickness of the SOI layer of a starting wafer is measured at a plurality of locations on the wafer. In embodiments, the measurements are used to determine a removal thickness at each respective location, e.g., an amount of the SOI layer to be removed at the location in order to create a substantially uniform ETSOI layer. In embodiments, a dynamic ion implantation is performed at variable dosage and/or energy in the SOI layer based on the removal thickness of the respective locations. The wafer is then oxidized to form oxide of varying thickness, and the oxide is etched. The resulting wafer has an ETSOI layer that is sufficiently thin and uniform for the 22 nm node, e.g., has a thickness of less than about 60 Å and a thickness variation of less than about +/−6 Å across the wafer. In this manner, implementations of the invention may be used to fabricate ETSOI wafers for use with the 22 nm node.

#FIG. 1 shows a semiconductor structure and process in accordance with aspects of the invention. More specifically, FIG. 1 shows a wafer 10 comprising a substrate 30, an insulator layer 35 formed on the substrate 30, and a semiconductor-on-insulator (SOI) layer 40 formed on the insulator layer 35. In embodiments, the substrate 30 and/or SOI layer 40 may be composed of any suitable semiconductor material, such as, for example, silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable materials include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion or entire layer may be strained. Moreover, the wafer 10 may be formed using conventional semiconductor fabrication techniques, including but not limited to bonded SOI, SIMOX, etc. However, the wafer 10 is not limited to an SOI wafer, and the teachings of the invention are applicable to any desired wafer, such as a bulk semiconductor wafer. Additionally, the insulator layer 40 may be composed of any suitable insulator (e.g., dielectric) material, such as, for example, silicon dioxide (SiO2). For example, the insulator layer 40 may constitute a buried oxide (BOX) layer.

#As depicted in FIG. 1, the SOI layer 40 has a nominal (e.g., average) thickness “t” which constitutes a distance from an interface 42 between the insulator layer 35 and the SOI layer 40 to a top 44 of the SOI layer 40 measured along a line that is substantially orthogonal to the interface 42. As further shown in FIG. 1, the SOI layer 40 has different thicknesses, e.g., t1, t2, . . . , tn, at different locations, e.g., L1, L2, . . . , Ln, as a result of the SOI fabrication process used to create the wafer 10. For example, a wafer made using conventional processing techniques may have an SOI layer with a nominal thickness in the range of about 300 Å to about 500 Å. Moreover, such an SOI layer may have a thickness variation (e.g., a deviation from the nominal thickness at any particular location) of about +/−45 Å, and may even be as high as about +/−55 Å. However, the invention is not limited to a wafer having an SOI layer 40 with these dimensions. Instead, an SOI layer 40 having any desired thickness and thickness variation may be used within the scope of the invention.