System and method to correct errors in data read from a source supplying streaming data
AssigneeMarvell International Ltd.
InventorsPantas Sutardja, Hong-Yi Chen
Life of this patent
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Abstract
A system including a read module and a processor. The read module is configured to read data from a source supplying streaming data and to correct errors in a first portion of the data using a first error-correcting module. The first error-correcting module is unable to correct errors in a second portion of the data. The processor is configured to correct errors in the second portion of the data using a second error-correcting module. An error-correction scheme applied by the second error-correcting module is different from the error-correction scheme applied by the first error-correcting module.
Claims14
A system comprising:
- a read module configured to
- read data from a source supplying streaming data, and
- correct errors in a first portion of the data using a first error-correcting module, wherein the first error-correcting module is unable to correct errors in a second portion of the data;
- and
- a processor configured to correct errors in the second portion of the data using a second error-correcting module,
- wherein an error-correction scheme applied by the second error-correcting module is different from the error-correction scheme applied by the first error-correcting module.
A system comprising:
- a read module configured to
- read data from a source supplying streaming data, and
- correct errors in a first portion of the data using a first error-correcting module, wherein the first error-correcting module is unable to correct errors in a second portion of the data;
- a processor configured to correct errors in the second portion of the data using a second error-correcting module,
- wherein an error-correction scheme applied by the second error-correcting module is different from the error-correction scheme applied by the first error-correcting module;
- a first-in first-out module configured to
- receive the second portion of the data,
- output, via direct memory access, the second portion of the data to a memory associated with the processor, and
- generate a first control signal based on an amount of memory available in the first-in first-out module;
- an arbiter module configured to
- adjust a priority of the processor or a priority of the first-in first-out module to access the memory based on the first control signal, and
- generate a second control signal;
- and
- a multiplexer configured to
- communicate with the processor, the memory, the first-in first-out module, and the arbiter module, and
- grant one of the processor and the first-in first-out module access to the memory based on the second control signal.
A method comprising:
- reading data from a source supplying streaming data;
- correcting errors in a first portion of the data using a first error-correcting module, wherein the first error-correcting module is unable to correct errors in a second portion of the data;
- and
- correcting errors in the second portion of the data using a second error-correcting module,
- wherein an error-correction scheme applied by the second error-correcting module is different from the error-correction scheme applied by the first error-correcting module.
A method comprising:
- reading data from a source supplying streaming data;
- correcting errors in a first portion of the data using a first error-correcting module, wherein the first error-correcting module is unable to correct errors in a second portion of the data;
- receiving from a first-in first-out module, via direct memory access, the second portion of the data in a memory included in a processor;
- generating a first control signal based on an amount of memory available in the first-in first-out module;
- correcting errors in the second portion of the data using a second error-correcting module, wherein an error-correction scheme applied by the second error-correcting module is different from the error-correction scheme applied by the first error-correcting module;
- adjusting a priority of the processor or a priority of the first-in first-out module to access the memory based on the first control signal;
- generating a second control signal;
- and
- granting access of one of the processor and the first-in first-out module access to the memory based on the second control signal.
Dependencies are inferred from the claim text.