Reducing read latency using a pool of processing cores

A system for reducing read latency in a read processing storage system using a pool of a plurality of CPU cores, comprising:

• at least one scheduler scheduling write operations, read operations, and read and write operations between the pool of the plurality of processing cores,
• at least one write cache, remotely connected to each of the plurality of CPU cores, assisting with the write operations;
• at least one processor device, controlling the at least one scheduler and the at least one write cache, and operable in the read processing storage system, wherein the at least one processor device:
• assigns to each one of the plurality of CPU cores for processing only one of write operations, read operations, and read and write operations that are scheduled for processing,
• sets a maximum number of the plurality of CPU cores for processing only the read operations, thereby lowering the read latency, and
• allocates a minimal number of the plurality of CPU cores for processing the write operations, thereby increasing a write latency, wherein upon reaching a throughput limit for the write operations that causes the minimal number of the plurality of CPU cores to reach a busy status, the minimal number of the plurality of CPU cores for processing the write operations is increased.

A computer program product for reducing read latency in a read processing storage system using a pool of a plurality of CPU cores, the computer program product comprising a computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:

• a first executable portion that assigns to each one of the plurality of CPU cores for processing only one of write operations, read operations, and read and write operations that are scheduled for processing;
• a second executable portion that sets a maximum number of the plurality of CPU cores for processing only the read operations, thereby lowering the read latency;
• and
• a third executable portion that allocates a minimal number of the plurality of CPU cores for processing the write operations, thereby increasing a write latency, wherein upon reaching a throughput limit for the write operations that causes the minimal number of the plurality of CPU cores to reach a busy status, the minimal number of the plurality of CPU cores for processing the write operations is increased.