Trans-capacitance amplifier with picoAmperes input biasing and large output swing

A differential trans-capacitance amplifier comprising:

• one differential operational amplifier, comprising one differential input, one differential output, and circuitry to set to a proper value the common-mode voltage of the said operational amplifier output;
• one differential input connected to the differential operational amplifier input;
• one differential output connected to the differential operational amplifier output;
• and
• two identical trans-conductance paths, the first path connecting the said positive differential input to the said negative differential output, and the second path connecting the said negative differential input to the said positive differential output, each said trans-conductance path comprising a cascade of at least two identical cells, each said cell comprising a differential MOS pair, the second transistor of each said pair and the first transistor of the next said pair being each connected as diodes, and connected together to a current source, the first transistor of the first said pair and the second transistor of the last said pair having transistors of the complementary type connected as an active load, the current sources biasing the said differential pairs and the said active load in the sub-threshold region, the drain and the gate of the first transistor of the first pair being connected to one of the said differential inputs having a certain polarity, the gate of the second transistor of the last said pair being connected to the said differential output having an opposite polarity.

A differential trans-capacitance amplifier comprising:

• one differential operational amplifier, comprising one differential input, one differential output, one control terminal, and circuitry to set to a proper value the common-mode voltage of the said operational amplifier output when the control terminal is connected to a signal substantially in phase with the common-mode voltage of the said operational amplifier;
• one differential input connected to the differential operational amplifier input;
• one differential output connected to the differential operational amplifier output;
• two identical trans-conductance paths, each path having differential inputs;
• wherein each trans-conductance path comprises a differential MOS pair, the second transistor of each said pair and the first transistor of the next said pair being each connected as diodes, and connected together to a current source, the first transistor of the first said pair and the second transistor of the last said pair having transistors of the complementary type connected as an active load, the current sources biasing the said differential pairs and the said active load in the sub-threshold region, the gate of the first transistor of the first pair of one path being connected to the gate of the first transistor of the first pair of the other path and further connected to a reference voltage, the gate of the second transistor of the last pair of each path being connected to one of the said differential outputs, and the drain of the first transistor of the first pair of one path being connected to the drain of the first transistor of the first pair of the other path and further connected to the said control terminal.

An integrated circuit processing the voltage across a sensing device, the said integrated circuit comprising:

• one terminal;
• one operational amplifier having its inverting input connected to the said integrated circuit terminal;
• circuitry which biases DC the said operational amplifier non-inverting input and provides a very low AC impedance between the said non-inverting input and ground;
• and
• a cascade of at least two identical cells, each said cell comprising a differential MOS pair, the second transistor of each said pair and the first transistor of the next said pair being each connected as diodes, and connected together to a current source, the first transistor of the first said pair and the second transistor of the last said pair having transistors of the complementary type connected as an active load, the current sources biasing the said differential pairs and the said active load in the sub-threshold region, the drain and the gate of the first transistor of the first pair being connected to the said operational amplifier inverting input, the gate of the second transistor of the last said pair being connected to the said operational amplifier output.