Soft-decision input generation for data storage systems
AssigneeWestern Digital Technologies, Inc.
InventorGuangming Lu
Life of this patent
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Abstract
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
Claims21
A solid-state storage device comprising:
- a non-volatile solid-state memory array comprising a plurality of non-volatile solid-state memory devices configured to store data;
- and
- a controller configured to generate multiple-bit log likelihood ratios (LLRs) associated with a memory location by at least:
- determining a reference bit stream stored in a reference memory location;
- performing a plurality of reads of the reference memory location, wherein each of the plurality of reads is performed at one of a plurality of voltage read levels;
- calculating 1-to-0 and 0-to-1 bit flip count data corresponding to each of the plurality of voltage read levels, the calculating based at least in part on the reference bit stream and bit values from the plurality of reads of the reference memory location;
- generating possible LLRs associated with the reference memory location based at least in part on the 1-to-0 and 0-to-1 bit flip count data;
- generating a sequence of LLRs based at least in part on the possible LLRs and on bit patterns from a multiple read operation on a target memory location;
- and
- decoding data from the target memory location using the generated sequence of LLRs.
In a data storage system comprising a non-volatile solid-state memory array and a controller, a method of generating multiple-bit log likelihood ratios (LLRs) associated with a memory location, the method comprising:
- determining a reference bit stream stored in a reference memory location;
- performing a plurality of reads of the reference memory location, wherein each of the plurality of reads is performed at one of a plurality of voltage read levels;
- calculating 1-to-0 and 0-to-1 bit flip count data corresponding to each of the plurality of voltage read levels, the calculating based at least in part on the reference bit stream and bit values from the plurality of reads of the reference memory location;
- generating possible LLRs associated with the reference memory location based at least in part on the 1-to-0 and 0-to-1 bit flip count data;
- generating a sequence of LLRs based at least in part on the possible LLRs and on bit patterns from a multiple read operation on a target memory location;
- and
- decoding data from the target memory location using the generated sequence of LLRs.
Dependencies are inferred from the claim text.