Multiplication of matrices using systolic arrays
AssigneeXilinx, Inc.
InventorsKaushik Barman, Parag Dighe, Ragahavendar M. Rao
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Abstract
In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.
Claims13
A matrix multiplication circuit, comprising:
- a plurality of systolic arrays;
- a pre-processing circuit coupled to the plurality of systolic arrays and configured to:
- decompose a first input matrix into a first plurality of sub-matrices;
- and
- input each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with a second input matrix;
- and
- a post-processing circuit configured to combine output of the systolic arrays into a result matrix;
- and
- wherein
- the pre-processing circuit is configured to decompose the second matrix into a second plurality of sub-matrices, each sub-matrix of the second plurality of sub-matrices including one or more rows of the second input matrix;
- and
- the pre-processing circuit is configured to input, for each systolic array of the plurality of systolic arrays, sequentially input two or more of the second plurality of sub-matrices to the systolic array.
A method of generating a multiplication circuit, comprising
- selecting a decomposition of first and second input matrices into sub-matrices based on criteria including a throughput value and dimensions of the first and second input matrixes, the selecting of the decomposition of the first and second input matrices, includes performing the steps of:
- determining numbers of resources needed to implement one or more systolic arrays to exhibit a throughput greater than or equal to the throughput value for a plurality of decompositions, respectively;
- and
- selecting one of the plurality of respective decompositions having a lowest of the determined numbers of resources;
- generating the one or more systolic arrays for multiplication of matrices;
- generating a pre-processing circuit that is configured to:
- decompose the first and second input matrices into a set of sub-matrices according to the selected decomposition;
- and
- input the set of sub-matrices to the one or more systolic arrays according to the selected decomposition of sub-matrices;
- and
- generating a post-processing circuit configured to construct a result matrix from the output of the one or more systolic arrays according to the selected decomposition of sub-matrices.
Dependencies are inferred from the claim text.